Z-cache: A new approach for computer graphics architecture

The Z-buffer algorithm is one of the most popular hidden-surface-removal algorithms. This research investigates a novel way to increase the performance of the algorithm when a processor is connected to a frame-buffer and Z-buffer.;It is common to use slow speed DRAMs to construct the buffers that may degrade the performance. Nobody has tried to accelerate the buffer access because the influence of the buffer memory to the total performance was unknown.;We invented new cache architecture, Z-cache, which is a dedicated cache memory for Z-buffer (and frame-buffer). To evaluate the performance, we constructed a trace driven simulation system which consisted of one trace generator and one or more superscalar processor simulators. Through this system, the impact of the Z-cache was measured.;Also, we invented a special flush technique, background flush. Because Z-buffer access has a distinct pattern, this flush mechanism takes advantage of the pattern, and the mechanism flushes a cache line when the use of the line is completed. In addition to the temporal and spatial locality, a cache memory can use access pattern as a locality. This mechanism reduces the frequency of line replacement which consists of flushing and loading. With background flush, the timing to establish the coherency between a line (which is going to be replaced) and memory takes place earlier than with the conventional method. This method saves communication time between the Z-cache and memory when the contents need to be switched.;Through the evaluation, we found that a very small Z-cache is good enough to increase the overall performance. A 128 bytes direct-mapped Z-cache with the background flush mechanism increases the performance by 3 to 7.5 percent. This increase corresponds to 1 to 2.25 frames per second for a 30-frames-per-second processor. The increase here is much more significant than that of a CPU with Z-buffer dedicated pipeline.;This research revealed not only the usefulness of a cache memory for Z-buffer access but also the efficiency of the pattern based flush mechanism.