Architectures and algorithms for MPEG video coding

The MPEG coding standard is becoming widely used in digital video applications such as digital versatile disk (DVD), high-definition television (HDTV), and digital satellite systems (DSS). Most early implementations of MPEG encoding and decoding systems were based on hardwired processors or single-function processors. However, as the functionalities demanded from such systems increase, such as in desktop computers, the added cost of the hardware components solely for MPEG encoding or decoding is difficult to justify.; In this dissertation, we discuss the parallel processor architectures and software algorithms that can improve the MPEG encoding and decoding speed. Design of processor architectures for MPEG encoding and decoding requires not only the analysis of MPEG algorithms in terms of the raw number of additions or multiplications, but more importantly, a careful study of mapping those algorithms to the target processor at the instruction level.; We first present the real-time MPEG-1 video encoder and decoder implementation on Texas Instruments TMS 320C80, also known as Multimedia Video Processor (MVP). We evaluate MVP's strengths and weaknesses on MPEG algorithms. We also propose architectural enhancements that could be made to MVP for further improving the performance of MPEG algorithms. We then present a parallel algorithm for variable-length decoding which has been difficult to map to parallel processors due to its sequential nature. We also present several methods of implementing the inverse discrete cosine transform (IDCT) on parallel processors. A new algorithm for computing IDCT called the symmetric mapped IDCT (SMIDCT) is also investigated for an efficient implementation on parallel processors.