| Hypercube has been the most popular topology for developing multiprocessor supercomputers because of its connectivity, regularity, symmetry, and algorithmic mapping properties. However, if a hypercube needs to be expanded at some future time, both hardware configuration and communication software of each node has to be altered because of the fact that its node degree is not constant. Thus each node in the hypercube must have a sufficiently large number of I/O ports so that the degree of each node could be increased with subsequent expansions. Due to the large number of I/O ports needed for the hypercube, it generally supports serial communication. Most of the time the system may never be expanded to its full capacity, causing non-utilization of significant number of I/O ports and hence IC pins. Due to such problems with hypercube topology, Thinking Machines Corporation has decided to revert to tree structure instead of hypercube topolgy for their latest multiprocessor machine.; In December 1987, Hwang and Ghosh proposed a new interconnection network called hypernet which has a constant node degree and is easily expandable. However, its component count increases unsymmetrically with increasing size. Also, the number and location of I/O nodes in each module is not fixed. Therefore, we have proposed a new topology called symmetric hypernets which grows very gradually with the increase in dimension and hierarchical level of the system. Further, the number and location of I/O nodes in each module is fixed and predominated, and thus is known at the time of chip design. Moreover, I/O nodes are placed uniformly among the processing nodes requiring fewer I/O nodes in each module with nearly the same performance. Also, this will result in a simple and more compact VLSI design for the chips and will facilitate parallel bit (8 bit or more) communication among the nodes. The addressing and construction rules are simple. The symmetric hypernet has been expressed with the help of various analytical formulas to determine how different components would affect system performance. Performance and reliability of symmetric hypernets has been evaluated and compared with other architectures. Mapping of algorithms for image processing and compute vision on symmetric hypernets is currently under study. |
