The reliability of ultrathin silicon dioxide

The kinetics of carrier trapping and breakdown in oxides of less than 5 nm was studied. It was found that electron trapping was negligible, but hole trapping was relatively high. An effective oxide trap density due to tunnel annealing was proposed. The rate equation of carrier trapping in the bulk oxide was presented in connection with the generated hole injection by anode surface plasmons. The voltage variation during a constant current test was analyzed using the hole trapping model and capacitance-voltage measured interface trap generation, and approximate values for the capture cross section and hole generation rate were extracted. Using the weak area breakdown model we found that the ratio of weak to robust area is about 5%.; The electrical characteristics of ultrathin oxides used in an x-ray lithography n-channel metal-oxide-silicon (NMOS) process grown at 700{dollar}spcirc{dollar}C and 950{dollar}spcirc{dollar}C were studied. Oxides grown at 950{dollar}spcirc{dollar}C had a lower interface trap density than 700{dollar}spcirc{dollar}C oxides, but 950{dollar}spcirc{dollar}C oxides are more sensitive to x-ray radiation damage. After 350{dollar}spcirc{dollar}C hydrogen annealing about 80% of the radiation damage in the form of interface traps was recovered.; Charge trapping and device degradation by Fowler-Nordheim (F-N) stress was studied with ultrathin gate oxide (5.5 nm) MOSFETs. With positive and negative F-N stress it is found that ultrathin oxides show negligible electron trapping and relatively high hole trapping. These results are due to the effects of tunnel annealing and reduced electron trapping in these ultrathin layers.; Oxide charge trapping and interface trap generation by hot carrier stress was studied with x-ray irradiated MOSFETs. Although the threshold voltage and transconductance were recovered after a hydrogen anneal at 450{dollar}spcirc{dollar}C, the irradiated and annealed devices were more susceptible to damage under hot carrier stressing. The latent damage was quantified using the various gate voltage hot carrier stresses. It is found that the major part of latent damage is related to oxide hole traps and interface traps. Electron trapping is present, but is less significant.