Research On Encoding And Decoding Algorithms And Efficient Implementations Of LDPC Codes For Satellite-Ground High-Speed Data Transmission Systems

With the increasing demand for space exploration missions and the development of high-resolution payloads,the amount of data transmitted by the satellite-ground link will be increased significantly.Low Earth orbit(LEO)satellites are widely used because of their low launch cost,small communication delay,high observation accuracy and wide coverage,how to achieve high-speed data transmissions using limited on-board hardware resources within limited transmission time has become the core problem that needs to be solved in the development of China's current spacecraft.As an important part of high-speed data transmissions,channel coding can improve the anti-interference performance and reliability of data transmission systems.Low-density parity-check(LDPC)codes are a class of powerful error-correcting codes with near Shannon limit performance and are widely used in fiber-optic communications,space communications,storage systems.However,LDPC codes usually have long block lengths with high complexity of their iterative decoding algorithms,besides,LDPC codes cannot achieve rate compatibility through puncturing like Turbo codes,therefore the application of LDPC codes in LEO satellites for high-speed data transmissions still face challenges.In this dissertation,to meet the demand of LEO satellite-ground highspeed data transmissions and relying on the Chinese academy of sciences space science pilot project,algorithmic and architectural level optimization are incorporated to design high-speed,efficient,low-complexity,rate compatible,reconfigurable,and low-power LDPC encoder and decoder,and the main work and innovations of the dissertation are as follows:1.A low-complexity and reconfigurable LDPC encoder based on the CCSDS standard is proposed,which handles the problem of high resource consumption of parallel encoder.To shorten the encoding latency,parallel encoding algorithm is proposed.By analyzing the structural characteristics of different parallel-degree encoding,a reconfigurable encoding scheme is realized.The optimized shift register adder accumulators are used,which reduce the hardware resources.The proposed encoder has been implemented on Xilinx FPGA.The experimental results show that the maximum encoding speed is up to 1 Gbps at 125 MHz.And resources of registers and look-up tables are reduced by 13.7% and 14.8% respectively,compared with the state-of-the-art encoders.2.In view of the time-varying nature of LEO satellite channels and the need for space communication devices to have low power consumption,a fast accumulated semi-parallel recursive(FASPR)LDPC encoding algorithm and an efficient low power LDPC encoder based on the DVB-S2 standard are proposed.To calculate the paritycheck bits fast and recursively,a new parity-check bits memory array is used,which achieves rate compatibility and increases the encoding throughput rate.By using the binary feature to simplify the parity-check bit calculation,the encoder is lower power consumed.The proposed encoder has been implemented on the Xilinx FPGA,and the experimental results show that the encoder is compatible with two code rates and three encoding parallelism,and the maximum encoding throughput is up to 1.104 Gbps at347.5 MHz,and the power consumption of the encoder is reduced by 21.7%.3.An efficient forward error correction(FEC)encoder based on the proposed efficient low power LDPC encoder for variable coding modulation(VCM)schemes of LEO satellite-ground communications is proposed,which can support three VCM modes with high efficiency.Hardware architecture implementation on Xilinx FPGA shows that the encoder can correctly switch between three VCM modes and the encoding throughput rate of the proposed FEC encoder can reach 1.19 Gbps at 389.5MHz.4.To handle the high complexity of the informed dynamic scheduling LDPC decoding algorithms,a low-complexity residual-based layered belief propagation(RBLBP)LDPC decoding algorithm is proposed.The residual is used as a metric to dynamically determine the update order of each iteration.The analysis and simulation results show that the algorithm has lower computational complexity,and has faster decoding convergence speed and better decoding performance compared with the traditional decoding algorithms.Aiming at the normalized min-sum algorithm(NMSA),an enhanced partially-parallel LDPC decoder is proposed,which increases the decoding throughput.First,the multi-diagonal matrix is split and the message is stored separately using a distributed storage strategy.Then,soft message corresponding to adjacent rows(columns)of the submatrix is stored in one memory entry,which exponentially increases the amount of message read/write from memory and node operations.Hardware implementation on Xilinx FPGA shows that the proposed decoder can achieve a decoding throughput of 1.02 Gbps at 250 MHz.Through software simulation,hardware testing,and comparison with the state-ofthe-art LDPC encoders and decoders,it is proved that the LDPC encoders and decoders proposed in this dissertation are feasible and efficient,and have higher application value in the future LEO satellite-ground high-speed data transmission systems.At present,the low-complexity and reconfigurable LDPC encoder proposed in this dissertation has been applied to high-speed data transmission system of the “Advanced Space-based Solar Observatory”(ASO-S)satellite of Chinese Academy of Sciences Space Science Pilot Project.The efficient FEC encoder has been applied to the VCM transmission system of the “Big Earth Data Science Engineering Project”(Cas Earth)scientific satellite of Chinese Academy of Sciences Space Science Pilot Project.The work of this dissertation has important engineering significance.