Analysis And Solutions For Negative Effects At Gallium Nitride(GaN) Transistor Application With High Frequency And Fast Speed Switching

With the increasing development and maturity of wide band-gap devices,gallium nitride(GaN)transistors are capable of fast switching speed and high switching frequency: fast switching speed means relatively low turn-on and turn-off time,which helps reduce the switching losses;High switching frequency operation can curtail the weight and volume of passive components in the converters.These features render GaN devices a promising technology to further improve the power density of the converter on transportation,renewable energy and telecom applications.However,the GaN-based converter did not show the obvious benefits of power density and reliability because of the negative effects caused by the fast switching speed and the high switching frequency of the GaN devices.The dissertation conducts comprehensive research on the impacts of the fast switching speed and high switching frequency on the converter design related to the gate drive,control circuits,power quality,and proposes correponding practical system-level solutions and design criterions to relieve the negative impacts.Although the research topic in this dissertation mainly focus on GaN devices,the scope of the discussion is not fully limited to GaN transistors but also for Si C MOSFET.Especially,the issues at multi-level converter caused by the fasting switching speed of Si C MOSFET are discussed and analyzed in details.Moreover,the proposed analysis methods and the developed solutions can be applied to any power devices which are capable of fast switching speed and high switching frequency.Before the design of GaN-based converter,it is necessary to characterize GaN HEMT in term of static performance and dynamic switching behavior.Dynamic switching behavior needs to be evaluated under the double pulse test(DPT)circuits.Compared to the conventional DPT,due to the fast switching speed of GaN devices,it must choose suitable current and voltage sensors with enough bandwidth and measurement accuracy to guarantee the effectiveness of the test.The dissertation discusses the different voltage and current sampling schemes and selects the high bandwidth single-ended high voltage passive probe and coaxial shunt to sample the drain-source voltage and drain current respectively.In addition,the way of connection between probe and testing point also has a tremendous influence on the testing results,the right way of connection under high frequency application is given in this dissertation.Based on the above foundation of accurate measurement,the dissertation shows GaN HEMT characterization results and changing trends under different junction temperatures.Moreover,the impacts of parasitics of the gate drive circuits,main circuits and package on dynamic switching behavior has been investigated,and it points out the dominant factor of turn-on speed is dv/dt while turn-off speed is di/dt.In terms of the negative effects caused by the fast switching speed and high switching frequency,the dissertation studies three aspects of this topic: 1.Output waveform quality;2.Special design issue for high frequency converter;3.Noise immunity of control and protection circuits.Under high switching frequency,the dead time and rising slope of PWM voltage caused by the charge of junction capacitance seriously affect the effective duty cycle of PWM voltage,which causes the distortion in the output waveform and the power quality issue in the ac power electronics systems.The dissertation analyzes the factors contributing to the distortion and gives the closed-form equation of PWM voltage distortion under different inductor current.The traditional way to compensate the PWM voltage distortion is to adopt the feed-forward scheme with the close-form equation,however,it requires real-time sampling and online calculation so that it is difficult to implement the conventional compensation scheme in the high switching frequency converters.The dissertation proposes a one-cycle base closed-loop control scheme.The proposed scheme is designed with a combination of digital and analog circuits,and the PWM voltage sampling is realized by the integrator and reference duty cycle is given by the DSP.The traditional one-cycle control hardware cannot integrate the input signal during turn-off interval,to improve the drawback of the conventional scheme,while the proposed scheme adds the monostable trigger to fast reset the integrator voltage,which enables the controller to compensate the distortion during turn-off interval.The experiment was carried out to verify the proposed scheme in a high switching frequency single phase inverter,and the experimental results show a good compensation effect.The conventional converter design criterions cannot solve some specific issues under fast switching speed and high switching frequency application.For instance,ANPC and T-type topologies are usually used in the low switching frequency and high power application,and these topologies enable to use low voltage rating devices to reduce the switching loss and conduction loss.Nonetheless,the research of these topologies major focus on modulation,EMI design related topics and does not pay much attention to the power commutation loop.With the application of wide band-gap devices,the switching frequency of multi-level topologies is also increased.The multiple commutation power loops in these topologies will induce many issues ignored in the slow switching speed application and lead to extra losses and the over-voltage issue of non-active switches.In addition,in dc converters,the design criterion in conventional LLC resonant converter only covers the minimum required deadtime and does not give the upper limit of the dead time.But the experimental results of the high frequency LLC converter show the unsuitable large dead time will also lose the fully zero voltage switching(ZVS)capability.Aiming to these special issues under high switching frequency converters,the dissertation gives a thorough analysis and design rules to relieve them.To obtain good control performance and reliability,it requires the accurate sampling circuits and stable protection circuits to ensure a longtime reliable operation.However,the common mode noise in the high switching frequency converter will cause a serious issue to control circuits since no specialized design is made to suppress the high frequency common mode noise.Moreover,the amplifier and comparator generally applied in the power electronics circuits do not have enough noise immunity to high frequency common mode noise,so the sampling circuits and protection circuits suffer the serious interference,and the power quality and reliability of converter are degraded in a high noise environment.The interactions and emissions of common mode noise between the power converter and control circuits are introduced in this dissertation,and to relieve this issue,the layout of the key sensor and the selection of sampling time are optimized,and the design of common mode filter is analyzed to suppress the noise.Furthermore,a fast device-level protection scheme with high noise immunity by active clamping is designed based on the conventional desaturation protection.