Study On Rfic Miniaturization And Impedance Transition Compensation Of System In Package

The pursuit of miniaturization, multifunction, low cost and low power is ever-lasting for electronic products, which makes the process improvement and system integration become the trends of development of semiconductor industry. Though the wafer industry is improving process according to the“Moore's law”,“Moore's law”is running to the extreme as the die scales down. System integration technology is the important technology to overcome the extreme of“Moore's law”. There are three kinds of system integration technologies: system in package (SiP), system on chip (SoC) and three-dimension IC (3D IC). SiP integrates passive components, antenna and multiple chips which have different function and different process in one package to realize a complex system. Compared to SoC and 3D IC technologies, SiP has the advantage of high integrity, good process compatibility, low cost and high reliability. The application prospect of SiP is extensive and the market demand of SiP is tremendous.Radio frequency integration circuit (RFIC) is an important component of SiP. Miniature RFIC can improve the integration and reliability of SiP. RFIC miniaturization becomes a hot research topic in recent years. There are two trends of development of RFIC miniaturization technology: component reusable technology and active inductor technology. Component reusable technology is that multiple transceivers share the same component such as ultra-wideband low noise amplifier (UWB LNA), ultra-wide tuning range voltage control oscillator (VCO) and phase lock loop (PLL) in one multi-mode/multi-frequency band chip. Active inductor is an active network that mainly consists of MOS transistors. Under certain DC biasing conditions and signal-swing constraints, the network exhibits an inductive characteristic. Compared with spiral inductor, active inductor has the advantages of large and tunable inductance, large and tunable quality factor, high self-resonant frequency and low silicon consumption. Using active inductor to replace the spiral inductor of RFIC can greatly reduce the chip area and cost.Signal integrity is a non-negligible problem in SiP. Impedance transition of signal links is the main reason causing the signal integrity problem. Some common transitions are microstrip to strip-line vias, microstrip to surface mounted technology (SMT) pad, DC blocking capacitors, connectors and so on. In low frequency band, these impedance transitions have small effect to system signal integrity. However these impedance transitions seriously degrade the signal integrity of SiP which always works in high frequency. To the best of our knowledge, there has no research report on eliminating this impedance transition by special design method.This doctoral dissertation proposes a new floating active inductor based on resistive feedback technology. A 0.5-11GHz CMOS UWB LNA which can be reusable in a multi-mode/multi-band system is also proposed. In order to further reduce the area of RFIC in SiP, all the spiral inductors in the UWB LNA are replaced by the floating active inductor proposed in this dissertation. Finally the impact of impedance transition of SMT pad and DC blocking multi layer ceramic capacitor (MLCC) on the signal integrity are analyzed, and then a compensation design method to eliminate the impedance transition of these transitions is proposed. The dissertation mainly consists of the following research work and results:1. The principle and implementation of the synthesis of active inductor using Gyrator-C networks is analyzed. A new floating active inductor structure based on resistive feedback technology is proposed. This active inductor is taped-out using TSMC 0 .18?m process. Test results show that the core active area is only 0.04 mm2, the maximum inductance is 33 nH and the maximum quality factor is 68. This active inductor can be used to replace the spiral inductors in RFIC. Based on this active inductor, a new linearity improvement active inductor using feed-forward current source technology is proposed. The linearity of this new active inductor is obviously improved at the cost of small extra power.2. A 0.5-11GHz CMOS UWB low noise amplifier using dual-channel shunt technique is proposed. Channel A of this UWB LNA uses inductive serial peaking technique to obtain flatness gain in 0.5-11GHz frequency band. Channel B uses resistive feedback technique to realize wideband input match. When these two channels are shunted together, a 0.5-11GHz flatness gain and input match can be realized. The thermal noise of channel B can be cancelled by channel A through noise cancellation technique. This UWB LNA is taped out using TSMC 0. 18?m process. Test results shows that the maximum gain is 10.2 dB, power is 14.4mW, the input return loss is better than 9 dB and the noise figure is 3.9-4.5 dB in 0.5-11GHz. In order to further reduce the area of the UWB LNA, all the spiral inductors of the UWB LNA are replaced by the floating active inductor proposed in this paper. Simulation results show that the performance of the UWB LNA based on the active inductor is similar to that of the UWB LNA based on spiral inductor, but the area is reduced by 60%. 3. The 3D structure of microstrip to SMT pad in SiP is modeled, and the impact of impedance transition of this structure on signal integrity is analyzed. Then a new compensation design method is introduced, with which the reference planes underneath the SMT pads are cleared to eliminate the impedance discontinuity. An analytical model is derived to compute the optimal clear parameters using conformal mapping. Finally this compensation design method is applied to DC block MLCC mounted on PCB. Simulation and measurement results show that this compensation design method can significantly improve the S parameter, time domain reflection voltage and eye diagram quality of MLCC mounted on PCB.