Rearch On Device Optimization And Circuit Design Based On Dual Threshold Negative Capacitance Independent-Gate FinFET

With the increasing demand for low-power integrated circuits in modern mobile devices,5G terminals and so on,low power consumption has become an increasingly important optimization target at different levels of integrated circuit design.In the device optimization,the leakage power dissipation of traditional devices is affected by sub-threshold swing,and sub-threshold swing is limited by the "Boltzmann tyranny" constraints further.The sub-threshold can not break the limit of60mV/dec at room temperature,making it difficult to further reduce the leakage power consumption of traditional devices.In order to break through this limitation,a variety of new devices have been studied.Negative capacitor devices can break through the sub-threshold swing limit without changing the traditional current transmission mechanism,and the power consumption of the device can be further reduced.Based on the goal of breaking the subthreshold swing limit and reducing leakage power consumption,this paper studies the negative capacitor independent gate Fin FET device from the aspects of device modeling,device optimization and its circuit design and optimization.The main contents of this article include:1.A new structure of a negative capacitor independent gate Fin FET device is constructed,and a device model for the negative capacitor independent gate Fin FET is established.Combining the advantages of negative capacitor transistors and Fin FET devices,the new structure of negative capacitor independent gate Fin FET is proposed,and through the study of the basic working principle and characteristics of the negative capacitor independent gate device,the surface potential equation and current equation are derived,and a new device model for the negative capacitor independent gate Fin FET is obtained.2.The dual-threshold negative capacitor independent gate Fin FET device is optimized.First of all,the independent gate Fin FET(called the baseline device)is optimized for gate workfunction and device size,and the high threshold device and low threshold device(a high threshold device is equivalent to the series of two single-gate devices,a low-threshold device are equivalent to the parallels of two single-gate devices),and the ability to process information for individual devices is improved.Stacking negative capacitive materials at the gate,the subthreshold swing and switching current ratio are optimized by selecting the ferroelectric material and stacking method,adjusting the size of the ferroelectric film,analyzing the performance characteristics of the current transfer and output characteristics,and obtaining the dual-threshold negative capacitive independent gate Fin FET device.Experiments results show that the subthreshold swing of the optimized dual-threshold negative capacitor independent gate Fin FET device has reached a minimum of 38mV/dec,breaking the limit of "Boerzman tyranny",and the on-off current ratio(Ion/Ioff)is 1082 times higher than that of the baseline device.3.A method for constructing compact logic circuit cells is proposed.Based on the characteristics of a single dual-threshold device with series or parallel operation of two signals,compact combined combinational logic cell circuits and D flipflop circuits are constructed,and a new structure of memory circuit SRAM is constructed.The simulation results of the proposed combinational cell circuits show that the power consumption can be reduced by up to76.6% compared to the traditional logic circuits and the power delay product(PDP)can be reduced by up to 78.4%,and the PDP of the two D flipflops are improved by 48% and 51%,respectively.The Mod-10 counters with the new structure of being constructed with compact logic cells and the SRAMs with new structure have also been greatly improved in performance.4.A comprehensive approach based on BDD technology is proposed.According to the BDD sub graph characteristics of the compact logic unit,the homogeneous sub graph of the logic function is searched,and the compact logic circuits structure of the performance optimization is obtained,so as to obtain the logical comprehensive method based on BDD technology.Using the proposed algorithm,the MCNC standard circuit is logically synthesized and compared with the optimization results of the standard synthesis tools ABC and DC.The results show that the proposed algorithm can significantly improve circuit performance,reducing the area by an average of 20.5% and 22.7%,while the power consumption is reduced by36.6% and 26.1% on average,and the PDP is improved by 40.6% and 31.7%.