Research On Analytical Fault Current Calculation And Fault Clearing Technology For Flexible Dc Grids

Modular Multilevel Converter-based(MMC-based)DC grids can improve the level of new energy consumption and are becoming the support for the new-typed power system with new energy as the main body.However,DC grids are vulnerable to DC faults.The weak damping characteristics of the DC grid result in fast-rising DC fault currents,which can easily cause the shutdown of the network,affecting the safe and stable operation of the system.Therefore,revealing the intrinsic mechanism of the DC fault and establishing a fast and selective fault clearing scheme is of great importance for the further development of the DC grid.However,the commonly used fault simulation methods are limited in revealing the physical nature of the faults,while the technical performance of DC breaker-based fault clearing scheme is superior but their large-scale application is limited by its high implementation costs.Aiming at these problems,this thesis studies mechanism-revealing-oriented fault analysis methods and technical-economical fault clearing technologies from the following four aspects:(1)Analytical calculation of fault currents for MMC covering the whole DC fault development process.The three-stage fault development process of the DC fault is analyzed.Regarding the transient stages,e.g.the capacitor discharging stage(Stage I)and the AC infeed transient stage(Stage II),an equivalent RLC model and a Thevenin equivalent model are respectively established,and the analytical expression of the transient fault current is derived.For the AC infeed steady-state stage(Stage III),the features of the arm currents are studied.Based on the constant relationship between the arm currents and the AC and DC side currents,the AC and DC side current expressions are obtained by solving the arm currents in segments.Using the derived expression,the non-linear variation mechanism of the fault current with the system parameters is revealed.The proposed steady-state expressions,together with the expression for the transient stage,constitute an analytical calculation method for MMC covering the whole fault process.Simulation results in multiple fault scenarios have verifies the effectiveness of the proposed analytical expressions.(2)Analytical calculation of transient fault currents in DC grids.First,the frequencydomain linearized DC fault superposed network for pole-to-pole fault is established.Then,a network order reduction method based on topology reduction and common branch decoupling is proposed.In the network reduction step,only the fault MMC and its adjacent healthy MMC are retained,simplifying the meshed network to an open-looped network.While in the common branch decoupling step,the common branch of the openlooped network is decoupled based on the high-frequency equivalence theorem,representing the network to the superposition of several two-order RLC circuits.As such,analytical expressions of the fault current are deduced.After that,a phase-domain line equivalent model is proposed to deal with the coupling between negative and positive lines under pole-to-grounds faults.Using the derived expression,we analyzed the mechanism by which the inductor limits the fault current.Simulations and experiments with multiple fault scenarios verified the effectiveness of the proposed approach.(3)Research on fault clearing methods using multi-port DC circuit breakers.The DC fault clearing mechanism based on DC circuit breaker is analyzed.A ring-connected bridge-type multiport DC circuit breaker is posed to overcome the high cost and lowreliability problem of the existing DC circuit breakers.First,the topology and the control strategy dealing with different types of faults are designed.Then,the electrical stresses of the breaker are analyzed,and the required number of power devices on each branch is determined.After that,a low-voltage three-port breaker prototype is built to verify the effectiveness of the proposed scheme.Finally,the technical and economical performances of the breaker are compared with existing schemes.The results show that the proposed scheme can handle the breaker’s inner faults,and has higher reliability.To protect a DC node connecting with three lines,the cost of the semiconductors of the proposed breaker is only 1/3 of the existing two-port breaker.(4)Parameter optimization of DC circuit breaker based on breaking stress analysis.The current commutation and interruption process of the breaker is firstly analyzed.Secondly,the breaker’s fault equivalent model is established and its electrical stresses are analytically calculated.Then,a parameter optimization method for the DC circuit breaker is proposed.A set of optimal parameter schemes for balancing the technical and economic performance of the breaker is obtained.Finally,the validity of the proposed analytical formula and the feasibility of the obtained optimization scheme are verified by case studies.With the technical and economic performances considered,the proposed parameter optimization scheme cannot only ensure the systems’ continuous operation but also provides more options for the configuration of DC circuit breakers in DC grids.