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Research On Front-end Electronics And Verification System Of CEE-MWDC

Posted on:2024-06-01Degree:DoctorType:Dissertation
Country:ChinaCandidate:J P XuFull Text:PDF
GTID:1522307166483734Subject:Nuclear technology and applications
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The Heavy Ion Research Facility at Lanzhou-Cooler Storage Ring(HIRFL-CSR)is the highest energy Heavy Ion accelerator in Asia.The CSR External-Target Experiment(CEE)is under construction,which is a charged particle spectrometer suitable for the measurement of heavy ion collisions and proton-heavy ion collisions.The main scientific objective of CEE experiment is to achieve near-full space measurement of charged particle products in heavy ion collisions in the CSR energy region,and to provide basic experimental data for scientific research on important scientific issues such as nuclear reaction kinetics,properties of compact object,high baryon number density QCD phase diagram,etc.The spectrometer is composed of several sub-detector systems.The three-dimensional track measurement of electrically charged particles in the front corner region is achieved by using the Multi Wire Drift Chamber(MWDC),which contains 3000 readout channels.The MWDC detector in CEE presents requirement for readout electronics in terms of high counting rate,high integration,and high resolution.The traditional readout electronics based on discrete components has disadvantages such as power consumption and integration level,which can no longer meet the requirements.While the readout electronics based on Application Specific Integrated Circuit(ASIC)chip,has become a development trend in the field of nuclear detection and particle detection.It realizes front-end signal processing,data processing and upload by using highly integrated,low-power ASIC chip and high-performance Field Programmable Gate Array(FPGA)logic chip.According to the electronic readout requirement of CEE-MWDC detector,this paper firstly discusses and designs different technical routes on the basis of comparing various front-end electronics and ASIC chips developed for MWDC detector.Secondly,the waveform digitization scheme with the Front-End Amplifier for MWDC(FEAM)as the core chip was selected.The research of 32-channels,high counting rate and large dynamic range front-end electronics(FEE)for MWDC detector as well as readout verification system are carried out.Finally,a complete multi-channel readout electronics system with high counting rate,high integration and high resolution is realized.The main work includes circuit design of front-end electronics of CEE-MWDC,circuit design of data acquisition system based on waveform digitization and firmware design of data online processing and energy information extraction algorithm.At last,the result of experimental tests shows that the Root-Mean-Square(RMS)of the electronic system channel baseline noise is less than1f C.The channel energy resolution is better than 2%,and the time resolution is better than 1ns(600f C input condition).In the range of 14f C to 900f C,the channel integral nonlinearity is better than 1%.Combined with the MWDC detector,the energy resolution of 55Fe source is better than 24%.The FEEs combined with the data acquisition system based on SCA chip to carry out the cosmic ray test,and the track residual distribution meets the requirements.All the test results show that the front-end readout electronics can meet the requirements of the MWDC detector readout,and provide a favorable technical support for the next large-scale electronics engineering machine development.
Keywords/Search Tags:readout electronics, ASIC, Field Programmable Gate Array(FPGA), on-line data processing, 32-channel ADCs, Multi-Wire Drift Chamber(MWDC)
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