Study On Quantum Transport Simulation And Performance-Enhancement Methods In Ultrathin-Body And Multi-Gate Transistors

Metal-oxide-semiconductor field-effect transistor(MOSFET)scaling has seen the arrival of the hyper-scaling era,in which improving device performance has become increasingly challenging owing to the tradeoff among device ONstate current,power consumption,and short channel effects.These metrics are functions of multiple dimensions and cannot be easily decoupled.Therefore,more research efforts are required for performance enhancement and device design optimization to meet the needs of next-generation technology nodes.This thesis is focused on the device physics,modeling,characterization and simulation analysis of ultrathin-body and multi-gate transistors at the quantum level.The main research goal is the discovery of solutions to enhance the performance of p-type ultrathin-body double-gate MOSFETs with ultrashort channel length and gate-all-around(GAA)nanosheet transistors for highperformance and low-power logic applications.The scientific contributions are summarized as follows.Firstly,a self-consistent non-equilibrium Green’s function(NEGF)-Poisson simulator is developed to study the quantum transport in ultrathin-body double-gate p-MOSFETs.The six-band k·p Hamiltonian is incorporated to accurately model the complicated valence band structure of the p-MOSFETs.Looking at the 5-nm technology node and beyond,short-channel effects and tunneling induce severe performance degradation.A systematic study is presented to optimize the channel thickness and confinement/transport orientation configurations for achieving high ON-state current,and lower subthreshold swing and tunneling ratio in double-gate MOSFETs.The results reveal that the(001)/[100] orientation results in a minimum tunneling current ratio of 25% at the gate length of 5nm,which leads to the best ON-current and subthreshold swing values.Meanwhile,to achieve good electrostatic control the channel thickness should be reduced,which means the quantum confinement should be strengthened.Secondly,doping engineering is introduced to further optimize the device performance and control the short-channel effects.The impact of doping profile/concentrations on performance metrics such as ON-to-OFF current ratio,subthreshold swing and switching delay are investigated for high-performance and low-power applications.The numerical results underscore the importance of using a Gaussian doping profile versus constant doping to enhance the performance of such ultra-scaled devices in terms of subthreshold swing,draininduced barrier lowering and source-to-drain tunneling.The selection of a particular damping factor in the Gaussian function can also be employed as a parameter in addition to the peak doping concentration for optimizing the device performance.The effects of source/drain doping profile and concentration on the electric field distribution in the transport and confinement directions are also examined.Thirdly,a comprehensive quantum transport study is performed for the GAA nanosheet transistors at a sub-3nm technology node.The GAA nanosheet transistors have emerged as a promising candidate beyond the 3-5 nm technology nodes due to the superior gate electrostatics and better power and performance tradeoff compared to Fin FETs.Since PMOS devices currently lag behind NMOS in their ability to drive current,channel engineering has been implemented into nanosheet transistors to improve PMOS performance.The effects of material(Si/Ge),strain,crystallographic orientation,and cross-sectional dimensions are deeply explored using the in-house developed simulator based on a selfconsistent Schrodinger-Poisson solver and the top-of-the-barrier model.A straindependent 6-band k·p Hamiltonian is incorporated into the model for more accurate calculations of the energy-momentum dispersion in the strain-perturbed valence band structure,where the curvature,energy shift and splitting of subbands are investigated in detail for hole transport properties.Furthermore,the effect of channel engineering is comprehensively analyzed by evaluating the density-of-states effective mass,average injection velocity,mobility,current density distributions and current-voltage characteristics.An effective performance improvement from 2GPa compressive stress is achieved in[100]/(001)and [110]/(001)channels,with a 7% enhancement of ONcurrent shown in Ge nanosheet transistors.While a wider nanosheet channel cross-section improves the drive current by increasing the effective channel width,a smaller cross-sectional width yields an average increase of 29% in terms of the ON-state injection velocity due to stronger quantum confinement.Finally,the vertically stacked nanosheet transistor is studied,which offers excellent layout efficiency and improved drain current.The accurate modeling and characterization of intrinsic capacitance are critical for analyzing the device performances,especially when the quantum confinement effects are dominant.On the other hand,the extrinsic performance of GAA nanosheet transistors is severely limited by parasitic capacitances that need to be considered.The intrinsic capacitance of the stacked nanosheet transistor is evaluated using the CV characteristics obtained from the self-consistent Schr?dinger-Poisson solver and the top-of-the-barrier model.While the parasitic capacitances are modeled using the conformal mapping technique.The model takes into account the innerfringe capacitance screening for Si and Ge channel materials by the inversion layer when increasing the gate voltage.The capacitive optimization is performed by studying different channel materials,geometric parameter variations,crystallographic orientations,and the number of vertical sheet stack.The ability of the effective nanosheet transistor width in a given footprint to drive the capacitive load is analyzed.In addition,the device performance metrics,including energy consumption and switching speed,are also evaluated.