Research On Design Of Integrated Circuit Cell For Single-event Charge Sharing Tolerance

Integrated circuits operating in space environment are extremely sensitive to radiation effects caused by radiation particles,and single event effects can lead to malfunction or failure of spacecrafts.With the rapid development of integrated circuits,the technology continues to shrink,the operating voltage and node capacitance continue to decrease,while the operating frequency and circuit complexity continue to increase,resulting in the increasing sensitivity of integrated circuits to single event effects.At the same time,the density of integrated circuits continues to increase,and the spacing between transistors continues to decrease.Single-particle-induced charges can be collected by multiple adjacent transistors,resulting in charge sharing or multi-node charge collection.In nanoscale technology,charge sharing has become the emerging challenge and hotspot for radiation hardened design.For combination logic circuits and storage circuits in integrated circuits,many existing radiation-hardened techniques or cell structures cannot meet the new reliability requirements,or even fail.Therefore,taking charge sharing as the core,this paper studies the hardened design of the basic cells of integrated circuits,including combinational logic cell,sequential logic cell and memory cell.Improving the radiation tolerance of basic components in an integrated circuit is very beneficial for improving the reliability of the whole system.In this paper,the radiation hardened by design approach is adopted to solve the new problems brought by multi-node charge collection at the nanoscale,and provide guarantee for the reliable operation of integrated circuit system.The work of this paper mainly includes the following aspects:(1)Research on design of combinatorial logic cell for single event transient tolerance.The influence of transistor distance,layout configuration,single particle incident direction and angle on the pulse quenching effect induced by charge sharing in the combinational logic cell are studied,and the mechanism of the pulse quenching effect is analyzed.Dummy gate enhanced charge sharing technique is proposed.By splitting the posterior-stage transistor into two parallel transistors and using dummy gate instead of shallow trench isolation,pulse quenching effect is enhanced and transient pulse width induced by single particle is significantly reduced.The simulation results demonstrate that the dummy gate enhanced charge sharing technique can significantly reduce the widths of the single event transients and effectively mitigate the single event transients generated by the cells.Compared with other radiation hardened techniques,dummy gate enhanced charge sharing technique can alleviate single event transients more significantly.Dummy gate enhanced charge sharing technique is available for hardening standard library cells.(2)Research on design of latch cell for single event double node upset tolerance.By analyzing the working principle and characteristics of the C-element,and the feedback relationship between the nodes in the latch cell using the node redundancy technology,a double node upset tolerant latch cell structure is proposed.When single or double node upset occurs on any node pair,the cell can keep the correct storage value,and the upset node or nodes can be driven back to the correct state by other nodes.Compared with the existing radiation-hardened latch cells with the same fault tolerance,this structure has the characteristics of low delay and low overhead,and has low sensitivity to process variations.(3)Research on design of flip-flop cell for single event effect tolerance.Analyze the sources of soft errors caused by single-event transient,single node upset and double node upset in edge-type D flip-flop with master-slave structure,and the common error detection techniques in flip-flops,two kinds of radiation hardened flipflop cell structures are proposed.The first cell structure can detect soft errors caused by single-event transient,single node upset and double node upset.The second cell structure can detect and correct soft errors caused single-event transient,single node upset and double node upset.Compared with the existing radiation hardened flip-flop cells,the proposed cells have the characteristics of high reliability and low overhead.(4)Research on design of SRAM(Static Random-Access Memory)cell for single event multiple node upset tolerance.The design principle of SRAM cell is studied,and the key problem of SRAM cell anti-single-event multi-node upset hardened design are analyzed,a multi node upset tolerant SRAM cell structure is proposed.The structure combines circuit level and layout level radiation hardened techniques,adopts node redundancy technique at circuit level,and uses redundant nodes to construct multiple feedback loops,so that the upset nodes in the cell can automatically recover the correct state.At the layout level,a variety of radiation hardened techniques are used to inhibit charge sharing between sensitive transistors.The simulation results demonstrate that the cell can tolerate single event multi node upsets.Compared with the existing radiation-hardened SRAM cells,the proposed structure has the characteristics of high reliability and high read/write stability.