Research On Key Technologies Of High Reliability Design Of Digital Chip Front-end

With the inclusion of satellite Internet in the national new infrastructure strategy,it has once again become a research hotspot and has received widespread attention both at home and abroad,and a large number of Internet constellation plans have been proposed one after another.In order to further reduce the cost and increase the mass production capability of satellites,traditional communication satellite payloads need to be chip-based(ASIC-based)and software-based.Thanks to the continuous progress in the design capability of integrated circuits(IC)and the rapid development of their manufacturing processes,the functions and performance of chips have been greatly improved,thus making it possible for ICs to be widely used in the field of satellite communications.As an important carrier of satellite Internet,the reliability of the chip plays a vital role in the safety and reliability of network equipment operation and the stability of the entire satellite constellation network.However,with the increasing development of ICs,the shrinking CMOS size and the globalization of the supply chain have brought potential impacts on the reliability of ICs.First,with the shrinking CMOS size,the unit density of the chip is increasing and the corresponding node voltage is decreasing,which will lead to the chip being more sensitive to the radiation environment and charge sharing effect.Satellite communication chips operating in space are highly susceptible to high-energy particle impacts,resulting in single-event upsets,multi-cell flip,and other problems that affect chip reliability.Secondly,CMOS size reduction will bring about an increasing power density of the chip,and the temperature generated by the chip during operation will also increase.The increase in temperature will increase the leakage current in CMOS and the voltage drop in power/ground network,which may lead to chip reliability problems such as time delay failure and logic error.Finally,with the globalization of the supply chain,a large number of third-party resources(such as third-party intellectual property,third-party manufacturers,etc.)are used in modern chip design in order to shorten the time to market and reduce the design cost of the chip.However,untrustworthy third-party resources are highly likely to include malicious logic such as hardware Trojans in the services they provide,and this high reliance on third-party resources brings about chip reliability problems.Based on this,this dissertation addresses several key technologies and related issues in the design of digital chip front-end with high reliability from the flow of chip design,and the main work and results are as follows.1.A Bit-width Variable and Low Latency Matrix Error Correction Code for protecting critical information in chips is proposed.Based on the background that the chip is more sensitive to radiation environment and charge sharing effect,a Bit-width Variable and Low Latency Matrix Error Correction Code(BVLLMC)is proposed to protect the key information in the chip for the problems such as weak antiradiation reinforced IP error correction detection capability,high coding and decoding delay,and limited data bit-width support in digital chips.The BVLLMC algorithm first divides the data to be protected into matrix form,then uses different codes to generate the corresponding check bits for rows and columns,and finally interleaves them by the interleaving scheme proposed in this dissertation.The experimental results show that BVLLMC can realize single-bit error correction,double-bit error correction and triple-adjacent-bit error correction,and can effectively solve the problems of single-particle flip and multi-bit flip caused by particle collision,and has strong radiation resistance performance.In addition,the BVLLMC can be used to protect data with bit width of 4n(n=2,3,4,...),thus adapting to scenarios with diverse data bit widths and high delay requirements.2.A convolutional neural network-based RTL-level power prediction technique is proposed.A convolutional neural network-based RTL-level power prediction technique CNN4PP(Convolutional Neural Network for Power Prediction)is proposed to address the problem that the existing power consumption results are extremely time-consuming to obtain,leading to increased design costs.The core idea is to perform a nonlinear fitting of the RTL simulation trajectory and the real power trajectory corresponding to the design by convolutional neural networks.First,the input design is simulated in a small number of scenarios and its power trajectory is obtained,and the power model corresponding to the design is learned based on the simulation trajectory and the power trajectory.Then,only RTL-level fast simulation is performed for the design to obtain its simulation traces in all scenarios.After inputting these traces into the learned power consumption model,the power consumption corresponding to the design can be quickly obtained.The experimental results show that the error between the power consumption prediction results of CNN4PP proposed in this dissertation and the actual power consumption given after layout wiring is within 15%,which can be used to guide the low-power design of the chip and greatly improve the speed of design iteration.3.The chip reliability problem in digital chip front-end design brought by IC globalization is studied.The TJFMAL framework,the TGNNU4TJ algorithm,and the RELIC-GNN algorithm are proposed for the problem that third-party resources employed in chip design are highly likely to add malicious logic to the services they provide to affect chip reliability and security,respectively.The reliability of the chip is improved by testing and evaluating the third-party resources used in the chip design.This part of the research mainly includes the following three aspects.First,a Trojan detection framework based on classical machine learning algorithm,TJFMAL(Trojan Detection Framework using Classical Machine Learning),is proposed to address the problems of data imbalance and low recognition rate in existing classical machine learning Trojan detection algorithms.The framework first analyzes some circuit structures generated by existing open source Trojan circuits and Trojan generation platforms,abstracts the templates of Trojan trigger circuits from them,and then filters the input circuits by template matching to balance the ratio of Trojan circuits to normal circuits.Second,the filtered nodes are input to classical machine learning algorithms such as Support Vector Machine(SVM)and Recurrent Neural Network(RNN)for classification.The identified Trojans are then extended according to their circuit characteristics.The experimental results show that the TJFMAL proposed in this dissertation supports a variety of different machine learning models,while improving the detection results by 10%over the original machine learning models.Second,to address the problems that traditional Trojan detection methods are poor in recognizing emerging Trojans,do not have portability,and have uneven classification performance,graph learning is introduced into the Trojan detection problem,and a two graph neural union network for Trojan detection algorithm TGNNU4TJ(Two GNN Union Network for Trojan Detection)is proposed.The core idea of this algorithm is to transform the original Trojan detection problem into a problem of node classification in directed graphs by converting the netlist into a directed graph in non-Euclidean space.Furthermore,considering the problem that graph neural networks have insufficient processing power for directed graphs,two graph neural networks are used to learn the two directions of nodes in the graph.The experimental results show that TGNNU4TJ can automatically extract the features of Trojan nodes without tedious feature functions compared with existing Trojan detection algorithms,while the recognition balance is improved by 23%.Third,designed IP cores are often sent to third-party vendors in chip design to complete DFT netlist generation and other tasks.To address the possible problems of inserting malicious logic and changing IP functions in the netlist generated by the third-party vendors,a graph neural network-based logic identification and classification algorithm RELIC-GNN(Efficient State Registers Identification and Classification with Graph Neural Network for Reverse Engineering).The core idea is to transform the logic recognition problem into a directed graph classification problem corresponding to the data path structure in the inverse netlist.The netlist is first partitioned by a data path structure extraction algorithm,then a graph neural network is used to generate a feature label for the directed graph corresponding to each path structure,and finally a clustering idea is used to classify these feature labels to distinguish data logic from control logic.The algorithm adopts an unsupervised learning approach to avoid the large time overhead of manual labeling and to solve the problem of classification accuracy degradation due to labeling errors.Experimental results show that RELIC-GNN can quickly and more accurately classify control logic and data logic in the netlist.Compared with existing algorithms,RELIC-GNN improves the accuracy by 12%and achieves time acceleration ratio of up to 50 times.