Design And Mechanism Research Of Electrostatic Discharge Protection Device For Low Voltage I/O Interface

As the semiconductor line width node reduces to the nanometer level,how to enhance the reliability of core circuit inside chip has become a problem that researchers must face.Among many factors that affect the chip’s reliability,electrostatic discharge(ESD)leading to failure accounts for up to 35%.In recent years,under the advanced low voltage process,ESD damage to the inside part of chip has become increasingly significant,which severely limits the enhancement and development of chip quality.Therefore,in order to enhance the ESD robustness of the whole chip,both enterprises and scientific research institutions have begun to focus on ESD protection designing inside semiconductor products.Based on two structural devices,the silicon controlled rectifier(SCR)and tunneling field effect transistor(TFET),this thesis takes theoretical knowledge of semiconductor devices,solving the problems of the ESD protection devices’ low holding voltage,high trigger voltage and high overshoot voltage at the I/O interface of the advanced low voltage process.The main contents are as follows:1.The holding voltage of the unidirectional SCR-based ESD protection devices will be reduced to about 2V after opening fully.when the unidirectional SCR-based devices are applied to the I/O interfaces under the working voltage of 3.3 V or 5 V,there will be the latch-up phenomenon.Facing the above problem,1)This thesis proposes a novel device named stacked-modified vertical SCR(SMVSCR).SMVSCR adopts the method of connecting multiple single devices in series,which effectively improves the holding voltage.In addition,the proposed device solves the problem of too high trigger voltage after stacking of single devices by floating the base of NPN transistor inside SCR,using silicide-treated N+ and P+ short-circuit technology and PESD implantation layer technology.2)Based on the low-voltage-trigger SCR(LVTSCR)ESD protection device,the device named LVTSCR with embedded shunt path(LVTSCR-ESP)is proposed.The generation of a shunt path on the device’s surface reduces the base current of the transistor inside SCR and weakens the positive feedback effect between transistors,so as to increase the holding voltage of LVTSCR and prevent it from latch-up.The above two devices are verified by simulation,tape-out and actual tests.2.The ESD protection device with a dual-direction SCR structure,facing the problems of high trigger voltage and high peak voltage under transient response,When it is applied to the I/O interface with positive and negative voltage of 1.2 V.Considering these phenomena,1)this thesis first proposes a new type of diode-triggered dualdirection vertical SCR(DTDVSCR)structure,which is completely symmetrical in both directions,the early trigger path in device is formed through the connection of diodes,NWELL resistance and silicide-treated N+ and P+ short-circuit areas.The proposed device reduces the trigger voltage and overshoot voltage,and satisfies the applications of the I/O interface with working voltage of 1.2 V.2)Optimizing the early trigger path of the DTDVSCR and proposing a modified diode-triggered dual-direction vertical SCR(MDTDVSCR)structure.The early trigger path of the MDTDVSCR doesn’t contain the long NWELL region,and when MDTDVSCR open fully,there are two current discharge paths in each direction,which further reduces peak voltage under transient response and turn-on time,increasing ESD robustness of the device.3)When the ESD protection device with a dual-direction SCR structure is equipped with a grounded Pguard ring(PGR)and applied to the area between I/O and GND,there is a problem of the holding voltage in reverse path deteriorating.An enhanced double finger dualdirection SCR(EDFDSCR)ESD protection device is proposed to improve the reverse holding voltage by inhibiting the parasitic path of PGR.The above proposed devices are verified by simulation,tape-out and actual tests.3.In the future advanced low voltage process,the ESD robustness enhancement of the ESD protection network based on the Point-TFET is not significant under TLPlike simulation.In view of the above problem,this thesis proposes Line-TFET and Ge-Source TFET with higher tunneling current to replace Point-TFET used in ESD protection network.The simulation results show that the ESD protection network with Ge-Source TFET is enhanced in the early stages of the pulse,but thermal instability exists in the late.It is found that the ESD robustness of the whole chip can be effectively improved by reducing the mole fraction of Ge in Ge-Source TFET and using the Si Ge-Source TFET-based ESD protection network,which also reduces the voltage at the I/O interface.Finally,the thesis also studies and analyzes the ESD discharge capacity of TFET based on materials from group III and V.The above designs and studies are demonstrated by parameters calibration and simulation.