Research On Successive Approximation Registers Time Interleaved Analog-to-Digital Converter

With the rapid development of modern communication and other electronic information technologies,the demand for high input bandwidth,high resolution and high sampling rate analog-to-digital converters in electronic systems is growing.Time Interleaved Successive Approximation Analog to Digital Converter(TI-SAR ADC)combines the characteristics of SAR ADC that is easy to be implemented by digital process and time interleaved(TI)architecture can multiply the conversion rate of analog-to-digital converters with multi-channel number interleaving.However,the accuracy of SAR ADC is affected by capacitance mismatch,the conversion rate is limited by serial quantization,and the performance of ADC is greatly limited by inter-channel mismatches,such as offset,gain,timing-skew and bandwidth mismatch in TI architecture.In this dissertation,taking successive approximation time interleaved analog-to-digital converter as the research object,based on the basic theory of SAR,TI and the calibration of TI-ADC,the architecture of TI-SAR ADC is optimized,and the ultra-high speed and high-linearity input-buffer(IB),ultra-high speed and high-linearity Track-and-Hold Amplifier(THA),high-speed and low jitter clock receiving circuit with duty cycle correction,High-speed,high-precision and low-power SAR ADC and mismatch calibration technologies.On this basis,a 12 bits 4GSPS THA-TI-SAR ADC is developed.The mismatch of the timing-skew in the TI-SAR ADC is eliminated through the THA in the analog front-end,and the key technologies proposed are physically verified.The main research work and innovation points of this dissertation are as follows:(1)Based on 28 nm CMOS process,the THA-TI-SAR ADC system architecture using non binary capacitor array(DAC)is studied.First,the integer,non-binary,segmented-bridge and split capacitor array SAR ADC is designed in this dissertation,a12 bits 250MSPS SAR ADC is finally realized by optimizing the setting time of DAC and improving the speed of SAR logic and comparator.Secondly,a large input signal swing and high-linearity THA with 4GHz sampling rate is designed,and the coupling capacitance(Cds)between the source and drain of the sampling switch in SAR ADC is reduced to enhance the isolation effect between THA and TI-ADC.In addition,the THA in the analog front-end eliminates the mismatch of timing-skew in TI-ADC.And the mismatch of the capacitance,offset and gain is calibrated by Least mean square(LMS)between channels.Finally,the THA driven a 12 bits 4GSPS THA-TI-SAR ADC under the above technologies.When the frequency of the input signal is 20.1MHz,SFDR is77.2d B,SNDR is 60.36 d B,ENOB is 9.73 bits,FOMS＿HF is 156.5d B under test results;When the frequency of the input signal is 1953.61 MHz,SFDR is 63.87 d B,SNDR is55.46 d B,ENOB is 8.92 bits,FOMS＿HF is 151.6d B under test results.(2)A high-speed high-linearity IB with high output common-mode voltage stability is proposed,and a high-speed high linearity THA with high output common-mode voltage stability is designed based on IB technology.IB uses stacked source follower NMOS to eliminate channel modulation effect,uses feedforward capacitor to suppress nonlinear current,uses deep N-well device to eliminate NMOS substrate bias effect,introduces gain-bootstrap cascade current source to provide high-quality input signals,and uses common mode feedback to stabilize output common mode voltage.Finally,under PVT(Process,Voltage and Temperature),the change of the output common-mode voltage is reduced from 200 m V to 1m V.The power consumption of the IB is 96 m W,VPP is 0.8V,SFDR reaches 69.3d B when the frequency of the input signal is 1581 MHz.THA is researched and designed on the basis of the IB technology.THA is composed of input-buffer(IB),high-linearity sampling and holding bootstrap switch circuit,output-buffer(OB).THA samples input signals and holds them for one cycle to supply 16 channel TI-SAR ADC for sampling and quantization,and eliminates the timing-skew mismatch in the analog domain.The output common-mode voltages of the IB and the OB vary equally in PVT.After sampling and holding by the bootstrap switch circuit,the output common-mode voltages of the two buffers cancel each other and stabilize the output common-mode voltage of the THA.Finally,under PVT,the change of the output common-mode voltage is reduced from 200 m V to 10 m V.When the sampling frequency of THA is 4GHz,VPP is 1.4V and the frequency of input signal is 1953.61 MHz,SFDR reaches 63.87 d B and the power consumption is 300 m W.(3)An adaptive asynchronous logic(AAL)high-speed SAR ADC technology and LMS mismatch calibration technology based on least square fitting method are proposed.According to the difference of the setting time of each capacitor in SAR ADC,the reset time of the comparator is adaptively adjusted through AAL to generate the optimal delay for each quantization of DAC.Compared with 12 bits traditional binary,Integer weight non-binary and the adaptive asynchronous logic proposed in this dissertation,the time utilization ratio of the setting time of DAC is 50.1%,68.7% and98.5% respectively,which effectively shortens the setting time of DAC and improves the ADC conversion rate.The source code value of SAR ADC and the ideal ADC output code value fitted by MATLAB are used to calibrate the mismatch of the capacitance and offset in SAR ADC by LMS,and the mismatch value is transmitted to the digital domain in the chip by SPI and solidified to achieve background correction.This technique is also suitable for calibrating the mismatch of capacitor,offset and gain in TI-ADC.The above two technologies are applied to 12 bits 250MSPS SAR ADC.Finally,when the VPP is 1.2V and the input signal is 120.41 MHz,the test values of SFDR,SNDR and ENOB are 76.08 d B,59.54 d B and 9.59 bits,respectively.(4)A high-speed low jitter clock receiving circuit with duty cycle correction is proposed.The clock receiving circuit is composed of the continuous time linear equalizer(CTLE),broadband amplifier and output buffer.The duty cycle correction circuit(DCC)consists of a charge pump,a low-pass filter,an integrator and a voltage-to-current circuit.Bandpass CTLE adopts three high-speed technologies: active negative feedback,negative Miller capacitor and source negative feedback,which expand the bandwidth,eliminate inter-symbol interference,suppress low-frequency noise,and improve the quality of the output clock signal.The DCC feedback path adopts a second-order duty cycle detection circuit,which not only significantly improves the range and accuracy of duty cycle correction,but also effectively reduces clock jitter.The output duty cycle can be corrected to 50 ± 0.1% within the input duty cycle range is 20-80% and under 1-5GHz.The clock receiving circuit consumes 3m W and RMS jitter 53.7fs under 5GHz and 1V power supply voltage.