Research And Design Of Physical Unclonable Function Based On FPGA

Integrated circuits are an important part of today’s world information systems,from the Internet of Things with low cost and flexible implementation characteristics,to the aerospace and defense fields that require precision and stability,and their applications are extremely versatile.However,the hardware security of integrated circuit-based systems is extremely lacking,and it is rarely actively discovered and successfully repaired as a weak link in a trusted system.In order to improve the security of the hardware system,it can be achieved through the hardware primitives provided by the underlying electronic devices themselves.As a new hardware security primitive,the introduction of physical unclonable functions（PUFs）provides a novel idea for solving hardware security problems and plays the role of"safety and hygiene".However,the existing PUF circuit scheme cannot take into account the circuit hardware complexity,hardware resource overhead and robustness,and several novel PUF circuit design schemes are proposed in this dissertation.This dissertation uses AMD Xilinx SRAM FPGAs,through theoretical analysis,structural design and performance evaluation,to study the key technologies such as the optimization of stimulus response pairs,the improvement of stability,the reduction of hardware resource consumption and complexity,etc.,to provide a new scheme for FPGA hardware security protection,and to provide reference for the implementation of integrated circuit security technology.Specifically,the main research contents and innovations of this dissertation are as follows:1.Aiming at the weaknesses of large resource cost and poor stability of the commonly used ring oscillator（RO）PUF,this paper proposes two schemes:reconfiguration XOR gate RO PUF（XC＿RO PUF）circuit design based on configurable delay line and multiple routing configuration RO PUF（CMR＿RO PUF）circuit design.Through the establishment and analysis of the configurable delay model,an optimization scheme is obtained which can increase the delay difference of RO pair to solve the poor stability of PUF output response.The XC＿RO PUF scheme uses XOR gate to replace the invertor in the traditional RO PUF,and forms different RO structures by dynamic configuration of excitation signals,so as to achieve the difference in delay and obtain stable PUF output response.Compared with the XC＿RO PUF scheme,CMR＿RO PUF increases the RO pair delay by adding configurable functions and path reroute mode to the traditional RO.Further,the multiple configuration data are deleted through the pre-screening scheme to find the data under the optimal configuration as the incentive response pair.The experimental results show that the XC＿RO PUF circuit has good uniqueness and can work stably in a wide range of temperature and voltage,and has good robustness.In addition,the XC＿RO PUF circuit can increase the output response per unit CLB up to 2¹⁴bits,which has a significant increase in resource overhead.On the other hand,CMR＿RO PUF has good uniqueness and uniformity,and achieves 100%stability in the voltage range of 0.8～1.2V and the temperature of-40～100°C.2.Aiming at the problem that most current researches fail to reduce the complexity of circuit design while pursuing the stability and uniqueness indexes of PUF circuit,a novel M＿RO PUF circuit scheme is proposed.At present,most of the PUF circuits based on FPGA are implemented by look-up table configuration,which leads to a tedious design process.This dissertation breaks through the conventional look-up table design idea and uses the inherent multi-channel selector resources in FPGA to build the gate circuit.Experimental results show that the proposed M＿RO PUF circuit is significantly improved in terms of resource complexity,stability and uniqueness compared with other structures designed in the literature.It is worth mentioning that the stability of PUF circuit is greatly improved when 49.85%uniqueness is obtained.3.Aiming at the problem that using the process deviation of lookups table as entropy source of PUF circuit in current research can not improve the performance of PUF well and reduce the resource cost to meet the demand of current lightweight equipment,a M＿RS PUF circuit scheme based on MUX unit as PUF entropy is proposed.The delay gate element is constructed by MUX element to maintain good symmetry and realize the PUF design of unbiased RS latch.The experimental results show that the proposed M＿RS PUF consumes less hardware resources while the uniqueness and stability are further improved.Each M＿RS PUF unit consumes 4 MUX units and 2 DFF units,and it has good portability on AMD Xilinx series FPGA.