| Time-interleaved analog-to-digital converter is a key component that contributes to the frequency increase and digitization of communication systems,such as high-speed data centers,millimeter wave pulse radars,and mobile communication base stations.TIADC plays a vital role in promoting the development of various electronic communication systems.Due to the non-ideality of layout design and chip manufacturing process deviations,the parameters of sub-ADC channels are different.The mismatch between channels will severely limit the SFDR(Spurious-free-dynamic-range),the SNDR(Signal-to-noise-distortion-ratio)and other performances of TIADCs.This dissertation is aimed at the problem of inter-channel mismatches of TIADCs and focuses on the digital foreground and background calibration techniques to eliminate mismatch errors.Therefore,the performance of TIADC is significantly improved.The main work and innovation of the dissertation are as follows:(1)Investigated the foreground calibration technology of the timing skew mismatch between TIADC channels and proposed a single-channel digital mixing based foreground calibration algorithm.It uses the mixing modulation effect of the local digital sine and the input sine signal to estimate the timing skew mismatch and configure parameters and perform error correction through digital filtering technology.The algorithm effectively solves the phase ambiguity problem in the foreground calibration algorithm and is not interfered by the offset mismatch between channels.For a 12-bit four-channel TIADC model,the RTL(Register transfer level)simulation results show that the amplitude of the timing skew induced spurs are suppressed to below-80d B after calibration.The SNDR and SFDR reach 71.6d B and 80.8d BFS,respectively.(2)Based on research of the background calibration technology of the timing skew mismatch between TIADC channels,three background calibration algorithms are proposed and cross-compared:1)A self-extracted cross-correlation function based background calibration algorithm is proposed.The algorithm can be applied to TIADCs with any number of channels,without the participation of any analog auxiliary channels and the process of solving the first derivative of the cross-correlation function.For a 12-bit four-channel TIADC model,behavioral simulation results show that 74d B of SNDR and 96.3d BFS of SFDR are achieved after calibration,respectively;2)A background calibration algorithm based on digital zero-crossing domain equalization is proposed.Compared with similar calibration algorithms,there is no need to add the comparator offset calibration in the anti-PVT and analog auxiliary circuits.For a 10-bit four-channel TIADC model,behavioral simulation results show that 60.8 of SNDR and 74.1d BFS of SFDR are achieved after calibration,respectively;3)A two-stage difference calculation based background calibration algorithm is proposed.Through the two-stage difference and matrix calculation on the output of adjacent channel sub-ADCs,the timing skew of each channel is solved,and the error is corrected through digital filtering technology.The proposed calibration algorithm does not need a dedicated derivative filter,meanwhile,the simultaneous calibration of all channels can be conducted at the same time without the limitation of calibration speed due to calibration sequence requirement in previous technique.For a 12-bit four-channel TIADC model,behavioral simulation results show that 74d B of SNDR and 100.7d BFS of SFDR are achieved after calibration,respectively;This dissertation cross-compared the above three calibration algorithms,The results show that the two-stage difference calculation based background calibration algorithm has the fastest convergence speed,the best calibration effect and relatively low design complexity.Therefore,it is designed and simulated at RTL.The results show that for a 12-bit four-channel TIADC model,the amplitude the timing skew induced spurs are suppressed below-80d B after calibration.The SNDR and the SFDR reach 71.7d B and 80.8d BFS respectively.The number of sampling points required when the mismatch parameter reaches convergence is only 4000 points.(3)Investigated the comprehensive calibration technology of mismatch between channels,gain and sampling time in TIADC,and proposed a foreground comprehensive calibration algorithm based on the same frequency digital orthogonal local oscillator.Compared with the existing comprehensive calibration algorithm,it avoids the setting of the analog auxiliary circuit.And there is no need to introduce complicated matrix and IFFT operations.Relying on the phase difference elimination technology and the approximate calculation of the arctangent function,the calibration performance is improved,and design resource is saved.The RTL simulation results show that for a12-bit four-channel TIADC model,the amplitude of the mismatches induced spurs are suppressed below-82d B after calibration,the SNDR of 72.6d B and the SFDR of 83.7d BFS are achieved,respectively.In this dissertation,the single-channel digital mixing based timing skew foreground calibration algorithm,the two-stage difference calculation based timing skew mismatch background calibration algorithm,and the comprehensive calibration algorithm based on the same frequency digital orthogonality local oscillator are designed and realized by RTL and FPGA.The hardware test system is established by a 12-bit 3.6Gsps TIADC evaluation board for measurement and analysis.The measurement results show that for the single-channel digital mixing based timing skew foreground calibration algorithm,SNDR and SNDR before and after calibration are increased by 7.8d B and 20.4 d B at 498MHz sinusoidal input frequency,respectively;For the two-stage difference calculation based timing skew mismatch background calibration algorithm,when the sinusoidal input frequencies at 498MHz and1448MHz,SNDR is increased by 8.8 d B and 15.6 d B,and SFDR is increased by 20.3 d B and 25.3 d B,respectively.For the comprehensive calibration algorithm based on the same frequency digital orthogonality local oscillator,when the sinusoidal input frequencies 498MHz and 1448MHz,the SNDR is increased by 27.4 d B and 24.5 d B,respectively,and the SFDR is increased by 35.7 d B and 30.7 d B,respectively.Furthermore,the amplitudes of spurs are suppressed below-76d B after calibration for all calibration algorithms.Finally,this dissertation designs the ASIC back-end for the two-stage difference calculation and same frequency digital orthogonality local oscillator based calibration circuit with TSMC 40nm process.The result show that the area of the two-stage difference calculation and the same-frequency digital orthogonality local oscillator based calibration circuit is 0.0456mm~2 and0.0560mm~2,respectively,and the power consumption is 0.9643m W and 1.8419m W,respectively. |
PDF Full Text Request