Research On Computation And Communication For The NoC-based Neuromorphic Processor

The human brain completes complex tasks with the polar average firing rate and extremely low power density,the most intelligent embodiment of human beings.Neuromorphic computing simulates neurobiological structures in the nervous system through Very Large Scale Integration to support the large-scale Spiking Neural Network(SNN).The neuromorphic processor is the hardware platform for neuromorphic computing,which can support the deployment of different types of SNNs to complete the processing of multimodal and unstructured data.Network on Chip(NoC)has the characteristics of high performance,scalability,and massive parallelism.Many neuromorphic processors adopted NoC as the communication architecture.The gigantic,concurrent and unpredictable communication characteristics of SNNs have specific design requirements for neuromorphic communication interconnection architectures.The diversity of SNN types and NoC designs provide more solutions for the design and optimization of interconnect architecture.We have encountered many independent or related problems and challenges in designing and optimizing the interconnection architecture of neuromorphic processors.It needs to consider the design requirements of SNN and NoC comprehensively.This paper conduct relevant research on the challenges encountered in designing the interconnect architecture of neuromorphic processors and proposes reasonable solutions for specific problems.To efficiently process the spike data stream of SNN,we design and implement a spike calculation engine based on an asynchronous circuit,which can support event-based convolution operation.We analyze the communication behaviour of various SNN models and their various requirements for NoC with the ambition of supporting the implementation of larger-scale neuromorphic processors and researching the functions,performance,and joint exploration of software and hardware in NoC.In terms of computation array,according to the convolution computation requirements of SCNN,the corresponding asynchronous computation array is designed and implemented;In terms of design space exploration,SNN chooses the appropriate NoC configuration scheme in the design space of NoC;In terms of routing protocols,we design and implement efficient NoC routing protocols and hardware architectures;In terms of hotspot prediction,we use LSM to predict the routing hotspots of NoC in the next timestep;In terms of joint exploration,this paper ensures the accuracy of LSM and improves the performance of NoC through joint design and exploration of software and hardware.The contributions are as follows:· We propose a computational array for SCNN based on asynchronous circuits.We adopt an AER event-based convolution algorithm for SCNN.An asynchronously driven spiking neuron is designed.We construct an asynchronously driven computing array based on the spiking neuron.The asynchronous computing array can support convolution operations based on AER events and adopt a pipeline method to improve computing efficiency.The experimental results show that the design can achieve a recognition accuracy of 98.0% for the MNIST AER dataset.During the filling and draining processes of the systolic array,the number of active PE units in our PE array is reduced.· We propose an SNN application-specific network-on-chip design space exploration framework.In order to find the most suitable NoC design solution under specific constraints for a particular SNN application,an NoC design space is constructed.We have made improvements based on the simulated annealing(SA)algorithm to increase the speed of exploration further.We apply the framework with 7 SNN applications to perform the NoC design space exploration.The framework can improve performance(Average Transport latency)by 54% to 93%.The BetterHistory SA algorithm speeds up the searching process by 1.5 to 8 times.· We propose path-based NoC routing protocols for neuromorphic processors.Firstly,we propose a congestion-aware adaptive routing algorithm based on Hamiltonian paths.The routing algorithm can adaptively select the routing direction according to the state of the network.The average latency of our algorithm was reduced and the throughput rate was increased.Secondly,we propose a path-based multicast routing considering the distribution of neurons on the NoC.We used 6 SNN models to verify the proposed path-based multicast.Compared with the unicast protocol,the running time achieves 5.1x speedup,the total hops and the max transmission latency are reduced by 68.9% and 77.4%.The experiments show that the maximum length of the multicast path is reduced by 68.3% and 67.2% Our multicast routing has improved performance in terms of average latency and throughput compared with DP or MP multicast routing.· We propose an LSM-based hotspot prediction model for NoC routing hotspot pre-diction for neuromorphic processors.The predictor extracts the relevant local and global states of the NoC at each timestep.Then we preprocess these states to extract the essential features.In addition,we also adopt the heuristic algorithm to search the hyperparameter of the LSM to improve the prediction accuracy.Evaluation results indicate that the LSM models can predict hotspot formation with an accuracy up to 89.36% and 90.19% for FSDD and NMNIST datasets,respectively.· We propose a hardware-aware LSM network generation framework.It takes the spatial information of the 2D/3D NoC platform as one of the factors that generate synapses between neurons.It also uses heuristic algorithms to explore the hyperparameters to improve the accuracy of the LSM networks.The experimental results show that the LSM networks generated by our framework could achieve the 93%and 95% accuracy for FSDD and NMNIST spike-based datasets,respectively.The average percentage of synapses connection of hardware-aware LSMs in the intracores has been increased(up to 20.7x for FSDD dataset under 3D NoC platform).The average synaptic length has reduced dramatically(up to 56.7% for the FSDD dataset under the 3D platform).