Researches Of Key Techniques In The Blocker-tolerated Receiver Front-end Systems

With the development of the Internet of Things（Io T）and the large-scale implementation of the Fifth Generation,the density of the smart device in the environment is exponentially increasing.The concurrent operation of different radios makes the wireless environment easier to be blocked.The traditional receivers employ off-chip Surface Acoustic Wave（SAW）filters to filter out the out-of-band blockers.However,the SAW-based solution limits the integration of smart terminals and cannot handle the adjacent channels blocker.For this reason,the SAW-less receiver front-ends have stirred the interests of researchers.Eliminating SAW leads to very challenging blocking requirements,the circuits have to ensure the quality of the signal under the strong interference.The design considerations related to selectivity,noise,and linearity become more crucial.This thesis focusses on the research of the key techniques and circuit designs of blocker-tolerated receiver front-ends systems.The main work and innovations of this thesis can be concluded as:（1）The charge sharing effect between capacitors at input and output node of passive mixer is studied and a charge-sharing-filter-based blocker-tolerated receiver front-end architecture is proposed.Taking advance of the charge-sharing effect,the proposed architecture can simultaneously achieve the 1^st-order complex filtering and down-conversion;Utilizing the adjoint network,a simplified model is established to guide the design of the charge-sharing filter,where the influences of design parameters are highlighted;A negative resistance is employed to enhance the quality factor of the proposed filter;In terms of circuit implementation,negative resistance can be integrated with the low-noise amplifier（LNA）.Built in a 28-nm CMOS process,the proposed front-end consumes only 400μW,while showing a noise figure of 6.8 d B and an out-of-band IIP3 of-0.35 d Bm,exhibiting excellent competitiveness in sub-m W receiver designs.This architecture has reached world advanced levels in terms of the figure of merit,which is defined by spurious-free dynamic range（SFDR）and power.（2）The influence of local-positive feedback and feedforward noise cancellation techniques are studied.The design considerations for LNAs under low-power constraints and noise optimization methods for RF front-ends have been proposed;A passive gain-boost technique has been employed in the proposed LNA to scale down the power needed for matching;Optimum local-positive feedback and feedforward coefficients in LNA have been analyzed.The noise contribution of each stage is analyzed.Through optimizing transconductance gain and noise figure for each stage,the overall noise of front-end is reduced;In LNA design,a current-reusing noise-canceling cascode topology has been proposed,which exhibits low noise,low power,large transconductance gain,and large output impedance.Simulation results indicate that the proposed LNA has a less than 3 d B noise figure and strong suppression of cascade stage.Built in a 28-nm CMOS process,the verified front-end with the proposed LNA consumes only 440μW,showing a noise figure of 4.8 d B,and is very competitive in terms of sensitivity and power dissipation.（3）The linearization techniques in front-ends circuits are studied and an improved highly linear front-end is proposed.A source-degeneration technique is employed in LNA to enhance its linearity;In order to overcome the influence of noise folding,an LC filter is added in the middle stage of the LNA;an improved highly-linear high-order filtering TIA is designed while the influence of capacitance in the feedback loop on performance is studied and the design parameters related to 1 d B gain compression point due to blocker（B1d B）are optimized;A verified28 nm CMOS front-end chip is processed and measurement results show a 7 d Bm B1d B and 6 d B noise figure,which has a promising prospect in high bit rates communication.