Study Of Temperature Field Model And Structure Of Silicon Carbide Device Based On Finite Domain Green Function Method

Silicon Carbide(SiC),owing to its exceptional material properties,has emerged as a next-generation semiconductor with high expectations.SiC MOSFET devices,as representatives of this semiconductor,exhibit remarkable advantages including high voltage tolerance,high power density,rapid switching capabilities and excellent thermal resistance.As a result,they are increasingly taking on vital roles in high-temperature,high-power applications.A significant proportion of power chip electrical characteristics are inherently tied to temperature,and many instances of performance degradation during operation can be attributed to excessively high temperatures.The unique operating conditions of SiC MOSFET devices often expose them to high-temperature,high-power scenarios,thus demanding stringent chip reliability and high-temperature system design.There are two significant challenges in the current research and high-temperature design of SiC MOSFET devices.Firstly,it neglects to account for the impact of non-uniform temperature field distributions on device degradation and failure.Secondly,it fails to effectively address junction temperature monitoring and protection in the hotspot areas of the chip.It is imperative to evaluate and monitor the junction temperature of these devices,whether for device reliability research or system high-temperature design.Presently,there is a deficiency in practical and user-friendly methods for evaluating chip temperature field distribution and high-precision real-time monitoring of hotspot temperature in SiC MOSFET devices.In light of these challenges,this dissertation focuses on the critical aspects of temperature field distribution evaluation and hotspot temperature monitoring for SiC MOSFET devices.The research incorporates theoretical models,experimental tests,device structures,and simulation designs.To begin with,the temperature field model based on the finite domain Green’s function(TFFG model)is established to foresee the two-dimensional temperature field distribution of the semiconductor chip.Building upon this foundation,the subsequent researches are undertaken.Investigation of the temperature field distribution and degradation failure mechanisms of SiC MOSFET power devices under high-temperature stresses.Design and manufacture of a highprecision SiC integrated temperature sensor capable of real-time monitoring of hotspot temperatures.Subsequent to testing,the results were aligned with the calculations from the TFFG model.Simulation of the Si/SiC heterojunction power MOSFET structure,with low working losses,and the validation of the benefits of this novel structure in reducing self-generated heat during working by the TFFG model.Here are the specific findings and innovations:(1)The temperature field model based on the finite domain Green’s function mothed is introduced,offering a pioneering application of the Green function method to heat conduction in SiC MOSFET power devices.The coupling relationship between heating power density function and non-uniform temperature field distribution of SiC devices is revealed by the TFFG model.This model includes two distinct algorithms,the electrothermal coupling step algorithm and the single-pass integral algorithm,designed to accommodate varying device working conditions.Furthermore,it incorporates heat conduction in the three-dimensional direction of the device into the two-dimensional definition domain,employing the RC thermal resistance network method and the nonuniform dynamic thermal resistance model,thus simplifying modeling and enhancing computational speed.Compared with the Comsol FEM simulation software,the rate of deviation of the results obtained by TFFG model is lower than 1.88%,and the computational speed is improved by 59.5%.(2)The mechanism for failure and degradation in SiC MOSFET devices under hightemperature stress of repetitive Unclamped Inductive Switching(UIS)is proposed.Additionally,it offers a novel perspective on the degradation failure mechanism of SiC MOSFET integrated with Schottky diodes(JMOS),especially under repetitive UIS hightemperature stress.This is the first time such insights are derived from the twodimensional temperature field distribution across the chip.Based the TFFG model,the temperature field distribution during the UIS test is computationally obtained.Integrated with experimental results,it is substantiated that Schottky contact barrier degradation in SiC JMOS devices during experiments are inhomogeneous.The Schottky contact barrie height reduces about 0.14 e V and the ideality factor increases 1.82.The degradation was notably more pronounced in the hotspot region with higher temperature,leading to a lower critical thermal breakdown temperature.Consequently,the failure of device occurs in the hotspot region.(3)A high-performance integrated temperature sensor integrated in SiC MOSFET device is proposed and manufactured.For the first time,this sensor offers a high-precision and real-time point temperature monitoring during SiC MOSFET working.This integrated temperature sensor is characterized by superior temperature measurement linearity,robust anti-crosstalk and noise capabilities,and high integratable.Its linearity reaches an impressive 0.9999,with temperature measurement range of 15-200 ℃.Its crosstalk interference with the main device is less than 1.87 ℃.It can efficiently monitor temperatures during SiC MOSFET operation.With highly tolerance of design and manufaction,the sensor can be miniaturized and integrated into SiC power devices and modules,enhancing temperature measurement accuracy within these modules while reducing overall system complexity.(4)The innovative Si/SiC heterojunction power MOSFET structures is proposed.The structures are optimized for low working losses and low working temperature which is validated through TFFG modeling.To address the low channel mobility issue of SiC MOSFET devices,two distinct power MOSFET structures are introduced,based on both planarand trench structures,capitalizing on the benefits of both Si and SiC materials.The electron tunneling layers and grid-controlled tunneling effects,effectively reducing hetero-interface resistance.The novel structures maintain the high breakdown voltage while significantly reduce the switchin losses.Compared with the conventional structure,the on-resistances of the Heterojunction Tunneling Vertical Double Diffusion MOSFET(HT-VDMOS)and the Heterojunction Double Trench MOSFET(HDT-MOS)are reduced by 65% and 20% respectively,and the gate-drain charges is reduced by 31% and 52%respectively.These comprehensive studies advance the evaluation and monitoring of junction temperatures in SiC MOSFET devices,introducing novel perspectives and methodologies for enhancing the reliability of SiC power devices.This research forms the foundation for optimizing the thermal management of SiC power devices based on temperature field distribution.