Van Der Waals Metal Integration Process And Polarity Control Of Two-Dimensional Transistors

In recent two decades,two-dimensional（2D）semiconductors provide great opportunities for the continued scaling and multifunctional application of new contemporary electronic devices owing to their atomically thin geometry structure,excellent transport properties,and tunable bandgaps.However,using conventional“high-energy”lithography/deposition processes are not compatible with 2D atomically thin lattices:conventional metal fabrication processes usually cause interface states and Fermi level pinning effects in contact region,leading to uncontrollable the metal-semiconductor barriers of the 2D transistors.Recently,van der Waals（vd W）contact geometry based on dangling-bond-free has developed.This vd W contact as a“low-energy”integration process can avoid aggressive metal vapour atoms from damaging2D delicate lattices and greatly retain the intrinsic properties of 2D contact region that is crucial for making high quality metal-2D interface.In this dissertation,using vd W integration method realizes clean and atomically sharp interface.Taking a step further,2D devices with complementary functions are constructed by modulating the interfacial coupling strength.At the same time,The polarity types of 2D transition metal dichalcogenide semiconductors are systematically investigated,realizing 2D logic functional devices.Finally,considering the limitation that current vd W contact can only be applied a few choices of metals（that can be laminated）,we develop a simple and universal vd W metal integration technology.The main contents are as follows:（1）The polarity types（n-or p-type）of 2D TMD WSe₂ and MoTe₂ field effect transistors（FETs）with different thicknesses are investigated.By using vd W integration of gold（Au）electrode,these FETs exhibit robust and optimized hole carrier（p-type）transistors behaviors regardless of their own thickness,which confirm that ideal band-matching can be achieved through vd W metal-semiconductor interface.This is in great contrast to the FETs utilizing traditional directly deposited Au contacts exhibit highly correlated with the thickness of 2D materials,clearly demonstrating transition from p-type to electron carrier（n-type）characteristic.The majority carriers between two approaches confirm the Fermi level pinning effect generated in thermal evaporation contact.（2）Combining vd W integration and evaporation integration methods,both PMOS（p-type metal oxide semiconductor）and NMOS（n-type metal oxide semiconductor）transistors are realized on the same WSe₂ flake.By connecting these two complementary FETs,a high-performance complementary metal-oxide-semiconductor（CMOS）inverter with a voltage gain of 340 as well as total noise margin more than 90%is realized.Furthermore,more complex logic functions of NAND and NOR are demonstrated by the simple polarity control strategy,which provides ideas for the design of high performance 2D electronics and CMOS logic circuits.（3）A scalable and universal vd W metal integration strategy is developed.Using thermally decomposed[poly（propylene carbonate）]（abbreviated as:s PPC）films as buffer layers between metals and semiconductors,different metals can be directly evaporated on top of PPC surface.After decomposing the PPC film by annealing,2D FETs with vd W metal contact are fabricated,exhibiting clean and atomical sharp metal-semiconductor interfaces and high-performance transistor characteristics.This vd W contact technology avoids bubbles or wrinkles during metal transfer and can be fabricated on wafer-scale substrates for various semiconductors.