| The rapid development of the Internet of Things(Io T)has driven the deployment of largescale wireless sensor networks for signal collection,processing,and exchange in various application scenarios,including environmental monitoring,automotive electronics,medical detection,and aerospace.Playing a crucial role as a bridge between the analog and digital domains in wireless sensor networks,Analog-to-Digital Converters(ADCs)have gained significant importance.As electronic devices in these application scenarios continue to evolve towards higher energy efficiency and integration,low-power and small-area ADCs have become a focal point of research in the field of integrated circuits.Leveraging the advancements in Complementary Metal-Oxide-Semiconductor(CMOS)process technology,ADCs have achieved higher integration levels,smaller chip area,lower power consumption,and significant improvements in bandwidth and energy efficiency.However,in advanced nanoscale processes,the intrinsic gain of transistors decreases,and the low power supply voltage limits the signal swing.These factors increase the design complexity of traditional analog circuits,rendering traditional architecture ADCs unsuitable for advanced CMOS processes.In contrast to voltage-domain ADCs,Time-to-Digital Converters(TDCs)implemented in the time domain primarily consist of logic gates as their fundamental circuit elements.Consequently,they can benefit from reduced CMOS logic gate propagation delays.Simultaneously,TDCs are not constrained by power supply voltage for input signal amplitudes.Lower power supply voltages,in fact,contribute to reduced power consumption and enhanced energy efficiency,making TDCs a promising alternative.However,TDCs are significantly affected by process,voltage,temperature(PVT)variations,and transistor mismatches,which limit their application to medium-to-low accuracy scenarios.Therefore,the hybrid ADC incorporating voltage-domain ADC and time-domain TDC features an advanced circuit architecture with high digitization and excellent process portability.This design has the potential to overcome the design limitations of traditional voltage-domain ADCs in advanced CMOS process technology,addressing the shortcomings in TDC quantization accuracy and achieving superior overall performance.In this context,this thesis focuses on the research and development of system architecture and circuit design methods for a novel hybrid-domain ADC based on voltage-time conversion and TDC quantization.The high-resolution Successive Approximation Register Analog-to-Digital Converter(SAR ADC)exhibits high power consumption and a large chip area due to its low noise comparator and high linearity capacitor array.To address these challenges,a two-step architecture comprising a coarse quantization stage followed by a fine quantization stage is commonly employed.To enhance overall quantization accuracy,the fine quantization stage can be realized using a noise-shaping ADC.This thesis has designed a two-step hybrid-domain ADC using a 65 nm CMOS process.It employs a SAR ADC as the coarse quantization stage and a second-order noise-shaping Time-to-Digital Converter(TDC)as the fine quantization stage.The TDC predominantly consists of logic gates,significantly reducing design complexity.To further optimize the power consumption and area of the SAR ADC,a novel Quatr-level switching timing algorithm is proposed in this thesis,which achieves zero-power quantization in the first three highly weighted quantization stages.Compared to traditional switching timing algorithms,the Quatr-level switching timing reduces the switching power of the capacitor array by 99.61% and decreases the required unit capacitance quantity by87.5%.For enhancing the Signal-to-Quantization-Noise Ratio(SQNR)of the TDC,this thesis explored pole optimization in the time domain.The proposed method adjusted feedback coefficients to alter the transfer function poles,constructing an optimal transfer function to improve SQNR within the signal bandwidth.By refining the structure of existing time register-based integrators and implementing precise control over feedback coefficients through selective feedback paths,this thesis introduced a pole-optimized second-order noise-shaping TDC in the time domain.The proposed hybrid-domain ADC achieved postsimulation Spurious-free Dynamic Range(SFDR)and Signal-to-Noise-and-Distortion Ratio(SNDR)values of 75.7dB and 71.5dB,respectively.Configurable-precision ADCs can cater to the signal processing accuracy requirements of various application scenarios,reducing development cycles and achieving high energy efficiency.Building upon the proposed time-domain pole optimization method,this thesis conducted further research to configure the Signal-to-Quantization-Noise Ratio(SQNR)by selecting different Oversampling Ratios(OSR)for the second-order noise-shaping Time-toDigital Converter(TDC).By obtaining different optimal transfer functions for varying OSR values,the thesis enables SQNR configuration.Simultaneously,optimizing SQNR for any OSR through pole configuration reduces the OSR requirement to achieve the target accuracy.To validate the effectiveness of the design approach,a configurable-pole hybrid-domain noise-shaping ADC was designed based on a 180 nm CMOS process.External control signals were employed to select poles and adjust the TDC’s transfer function.A Voltage-to-Time Converter(VTC)converted the sampled voltage signal difference into time intervals,feeding them into the TDC for quantization.Since different poles correspond to distinct combinations of feedback coefficients in circuit implementation,the proposed hybriddomain ADC consolidated multiple sets of feedback coefficient combinations into a single loop,reducing power consumption and increasing integration.To simplify the circuit structure of traditional gated delay units,a novel Single Fan-out(SFO)gated delay unit was introduced.Simulation results demonstrated that compared to traditional gated delay units,the SFO gated delay unit exhibited a fourfold reduction in propagation delay and a 74%decrease in power consumption.The proposed hybrid-domain noise-shaping ADC underwent chip verification,with a chip area of 0.248mm2.The power supply voltages for the voltage-domain and time-domain sections were 1.8V and 1V,respectively.Three precision modes with OSR values of 200,100,and 50,corresponding to optimal pole distributions,were configured.Test results indicated that at a sampling frequency of 10MS/s and an input signal frequency of 5.6KHz,the power consumption for the three modes was506μW,510μW,and 502μW,while the SNDR was 64.5dB,56.1dB,and 51.2dB,and the dynamic range was 68 dB,58 dB,and 53 dB,respectively.These results validated the feasibility of the proposed architecture.Dynamic ZOOM ADCs dynamically adjust the reference voltage range of the fine quantization noise-shaping ADC in response to variations in the output results of the coarse quantization Successive Approximation Register ADC(SAR ADC).An overload range factor is introduced to extend the reference voltage range for error calibration,reducing the requirements for comparator noise and capacitor matching in the SAR ADC and thereby decreasing power consumption.In this thesis,a hybrid-domain dynamic ZOOM ADC was proposed based on a 180 nm CMOS process.It employs a 5-bit SAR ADC as the coarse quantization stage and a first-order noise-shaping Time-to-Digital Converter(TDC)based on gated delay units as the fine quantization stage.The overall circuit adopts a highly digital architecture,significantly reducing design complexity.Addressing the common gated skew errors in gated delay units,this thesis established a model for the generation process of gated mismatch errors in Single Fan-out(SFO)gated delay units and proposed an error calibration method for averaging gated skew errors.Simulation results demonstrated that the proposed error calibration method can reduce the magnitude of gated skew errors significantly,enhancing the performance of the noise-shaping TDC.The proposed hybrid-domain dynamic ZOOM ADC underwent chip verification,with a core chip area of 0.51mm2.The voltage-domain circuit operated at a power supply voltage of 1.8V,while the time-domain circuit operated at 1V.Test results indicated that at a sampling frequency of 10 MHz and an Oversampling Ratio(OSR)of 500,it achieved a Signal-to-Noise-and-Distortion Ratio(SNDR)of 87.88 dB,a dynamic range of 96 dB,and consumed 811μW of power,with a Figure of Merit(Fo MS)of 166.91 dB. |
