High-mobility Channel Transistors And Compute-in-memory Ferroelectric Transistors For High-energy Efficiency Integrated Circuits

Over the past 50 years,integrated circuit technology and industry have developed rapidly according to Moore’s Law.However,as CMOS process nodes enter sub-10 nm,power consumption and computational power have become key bottlenecks for continuing Moore’s Law.Means to further improve the energy efficiency of integrated circuits are becoming increasingly scarce.The use of high-mobility channel materials,such as Ge and InGaAs,can achieve lower operating voltage,lower power consumption and higher energy efficiency for integrated circuits.Currently,the main factor limiting the improvement of integrated circuit computing power is the separated storage and computing cells in the von Neumann architecture.Ferroelectric transistors are widely studied devices for achieving high computing power in non-von Neumann architecture in-memory computing integrated chips.This paper focuses on the research of high mobility Ge and InGaAs channel MOSFETs,integration technology,and FDSOI FeFET devices for high computing power in-memory computing.The main research results are as follows:1.A process implementation method for high-performance ZrO₂ gate dielectric Ge channel nMOSFETs was investigated and developed.Based on the fabricated ZrO₂-based Ge nMOSFETs,the effects of different passivation treatments on device performance were studied.Through the characterization and comparative analysis of their electrical properties,the excellent scaling potential of ZrO₂ high-κdielectric and the improvement effect of post-oxidation treatment with Al₂O₃ as the blocking layer on mobility were verified.Ge nMOSFET devices with an EOT as low as 0.59 nm were achieved by using ZrO₂ as the gate dielectric layer on unpassivated Ge substrate.However,the unpassivated devices exhibited poor mobility due to severe interface roughness scattering.O₃ passivation prior to ZrO₂deposition can effectively improveμ_eff,butμ_eff still degrades rapidly at high fields due to the mixing of ZrO₂ and GeO_x.Inserting an Al₂O₃ blocking layer for ozone oxidation not only achieved passivation of the interface but also blocked the mixture of ZrO₂ and GeO_x,resulting in the highest electron mobility（795.24 cm²/V·s）.However,it inevitably increased the EOT,and further reducing the thickness of the Al₂O₃ blocking layer is expected to achieve a lower EOT while maintaining a highμ_eff.2.The effects of heat treatment on the performance of Ge nMOSFET devices were analyzed and studied.Decoupled analysis was conducted on the influence of heat treatment on the gate stack layer and the source/drain parasitic resistance based on ZrO₂-based Ge MOSCAPs and nMOSFETs with the same stack structure.Parameters related to gate stack quality,including interface density,slow trap density,and EOT,were extracted from MOSCAPs.The results showed that the interface state density in the bandgap and slow trap density increased with increasing PMA temperature from 350°C to 500°C.Under the PMA condition of 400°C,the MOSCAPs had the lowest EOT due to the increase in dielectric constant.Meanwhile,the effect of PMA on parasitic resistance was analyzed from Ge MOSFETs,and the results showed that the Ge nMOSFETs processed at 400°C PMA had the lowest R_SD.By optimizing the gate stack layer and source/drain resistance,the Ge nMOSFETs processed at400°C PMA obtained the highest drive current,showing about 50%and 80%current improvement compared with the devices processed at 350°C and 500°C PMA,respectively.3.The PBTI reliability of Ge nMOSFET devices was investigated.Based on the preparation of ZrO₂-based Ge nMOSFETs,the effects of the interface layer,high-κdielectric thickness,and PDA treatment on the PBTI reliability of the devices were studied.The results showed that PBTI degradation in Ge nMOSFETs was attributed to the generation of interface traps and the capture of high-κbody traps.Interface traps were distributed at the IL/high-k and Ge/IL interfaces,resulting in the degradation of g_maxwith V_THshift.The SiO₂ IL interface showed a higher carrier-defect decoupling factor（γ/n）and a larger 10-year PBTI lifetime overdrive voltage.For Ge nMOSFETs with different high-κthicknesses,the decrease in high-κdielectric thickness resulted in a lower initialΔV_TH,but had little effect onγ/n.For samples treated in different PDA atmospheres,the PDA treatment underO₂ significantly improvedγ/n compared with that under N₂,which might be related to the production of positive polarons on the GeO_x/Al₂O₃ interface underO₂ annealing.4.The integration of high-mobility CMOS and optoelectronics was studied.InGaAs materials have higher electron mobility than Ge,and high-mobility InGaAs/Ge CMOS can continue to drive Moore’s law along the“More Moore”by improving the drive current.The study focuses on the process flow of high mobility and low interface state InGaAs nMOSFET and Ge pMOSFET that are compatible with the process.The experimental results show that InGaAs nMOSFET exhibits good electrical characteristics,including a high peakμ_eff（3777.79 cm²/V·s）and low D_it(1.1×10¹¹ cm^-2e V^-1),by using the buried channel method and fine interface treatment.For Ge pMOSFET,the native oxide is removed and the channel surface is smoothed by using self-limiting etching through thermal oxidation and wet etching.The surface is passivated through ozone post-oxidation,and the internal defects in the high-κdielectric and related Coulomb scattering are reduced through optimized deposition and annealing treatments,achieving high-performance Ge pMOSFET with a peakμ_eff of 684.29cm²/V·s.The capacitance characteristics show low D_it and EOT.The proposed process method provides a reference for achieving high-performance InGaAs/Ge CMOS integration work.Based on the implemented MOSFETs,optoelectronic integration of electronic devices and photonic devices is realized using Flipchip hybrid integration and single-wafer epitaxial integration technology.5.Transistor-type nonvolatile memory devices for low-power applications were prepared and analyzed.FDSOI and FeFET technologies are combined and researched to develop the implementation methods of FDSOI FeFET and its NAND array.Based on the dual-gate characteristics of FDSOI FeFET,two read-write modes that can be used to improve the performance and reliability of FeFET and NAND arrays are proposed.1)ferroelectric gate writing and reading,and the bottom gate is biased when reading.This write/read mode can achieve flexible modulation of HVT and LVT to reduce the read voltage and improve the durability of the ferroelectric gate.For the NAND array,complete control of the shared channel can be achieved by biasing the back gate,which can make the unselected devices on the same Bit Line all are“on”or“off”,avoiding reading interference errors caused by repetitive V_pass on the ferroelectric gate.2)ferroelectric gate writing and bottom-gate reading.The separated read-write path operation mode can realize a rapid increase in MW through the MOS capacitance coupling of the ferroelectric gate and bottom gate,while also improving the durability.For Ge substrate ZrO₂-based MIFET,the possible source of mobile ions was verified to be GeO_x through different surface treatments.Furthermore,the storage window characteristics of MIFET were characterized in the temperature range of 77 K to300 K,and the results showed that MIFET has good temperature immunity compared to HfO₂ FeFET.