Research On Hardening Techniques For Key Modules In Microprocessor Against Single Event Effect

Microprocessor is a key part of electronic system to realize data computation and processing,which includes complex combinational logic circuit and sequential storage cells.Microprocessors working in space environment are vulnerable to the incident of high-energy particles and the radiation effect occurs,which can cause errors in data operation and illegal jump or repeated execution of instructions,seriously threatening the normal execution of spacecraft missions.When the circuit modules are incident by high-energy particles,single event effect(SEE)will be generated,resulting in single event transient(SET)and single event upset(SEU).Soft errors caused by SET and SEU are the main source of microprocessor failures;meanwhile,as the process size decreases,the circuit modules become more sensitive to them.In this dissertation,radiation hardened design of the key modules including pipeline,Cache storage,and clock distribution network in microprocessor against single event effect is studied.More effective hardening techniques are proposed.Main contents are organized as following:(1)Research on hardened design for pipeline.Pipeline is the core of microprocessor to realize the function,and fault-tolerant design of D flip-flop is the main methods to hardening pipeline.Aiming at the problem of performance overhead and design complexity in hardening pipeline caused by fault-tolerant D flip-flop cell,in this dissertation,a low-overhead SET and SEU fault-tolerant D flip-flop(SETU-TOFF)is proposed.The cell uses pulse clocks to achieve temporal redundancy,which can remove the timing delay in processing SET faults from the circuit path to reduce the performance overhead caused by hardening design;uses Latch structure for spatial redundancy to handle SET and SEU errors,and the area and power consumption overhead can be reduced.Simulation results show that compared to the flip-flops with the same fault-tolerant capability,SETU-TOFF has advantages in area and power cost,and has lower design complexity because no error recovery control circuits are needed when it is applied to pipeline hardened design.In addition,an effective delay cell is proposed to provide pulse clocks for SETU-TOFF cells in hardened design.The proposed delay cell uses saturated transistors to obtain delay.Compared with the traditional inverter chain and the delay cell provided by technology library,it can highly reduce the area cost and power consumption when providing the same delay.Using the proposed SETU-TOFF and delay cell,the pipeline hardened design of Open RISC microprocessor is implemented,and fault injection experiments are carried out.Experimental results show that the SETU-TOFF can effectively protect the pipeline and resist the SET and SEU faults.(2)Research on hardened design for Cache storage with high performance.Cache is a key component to improve microprocessor performance.However,the storage cells of Cache are highly sensitive to SEU.Aiming at L1 Cache with higher performance requirements,this dissertation proposes a write-buffer scheme to solve the problem of CPU time occupied by early write backs of the existing replication-based schemes,and to realize full protection for both tag bits and data bits.The write-buffer scheme is implemented with double replication Caches.The two replication Caches are designed to work alternately in replication mode and writeback mode to realize the data replications and early writeback.Error detection is implemented with 4-bit interleaved parity check code to detect 4-bit burst errors.When an error is detected,the data is reloaded from the lower memory level or Write-Buffer in the form of a forced Miss to achieve error correction,where the decoding of parity check can be executed in parallel with the Tag matching of Cache access,thus avoiding the impact of decoding on Cache access latency.Furthermore,the early writebacks can take advantage of the idle time when the lower-tier storage is not being accessed and writes data back to the lower-tier storage in the background,thus avoiding the additional clock cycles overhead.Simulation results show that the proposed write-buffer scheme does not affect Cache performance,and on the contrary,it can improve system performance because of the background writebacks.Compared with the similar scheme,it can reduce the impact of hardened design on performance and power consumption,and is more attractive for Cache hardened design with high-performance.(3)Research on hardened design for Clock distribution network.Clock signal is the most important signal in microprocessor,with high operating frequency and wide distribution.It is transmitted to the sequential cells in the circuit through clock distribution network,to control the data storage and transmission.Aiming at the more and more serious SET problem in clock distributed network,a SET-tolerant clock inverter cell is proposed for clock distributed network hardened design,to solve the problems of weak anti-SET capability and short-circuit current in the existing cells.Simulation results show that compared with the existing clock cells,the proposed cell can not only prevent the SET pulse from propagating in clock distribution network,but also cut off the short current between the power source and ground caused by SET pulse,so it can provide more secure protection for clock distribution network.Moreover,the proposed cell can effectively mitigate the problem of single event multiple transients caused by multiple node Charge collection via the source extension technique at layout.The application test of the hardened clock distribution network of Open RISC microprocessor shows that the proposed clock inverter cell can effectively prevent the SET pulse from being transmitted to clock output;clock distribution network is effectively protected by the cell.