Study Of Hardware System For Motor Cortical Neural Decoding In Rats

Brain-computer interface research has become a hot field of neural engineering. The research could help the disabled to restore their motor and sensory function, and promote the development of neuroscience and information science. Implanted electrode technology can provide high-quality neural signals and thus the potential for increased performance relative to non-invasive approaches. The main purpose of this thesis is to study the hardware system for motor cortex neural decoding experiments in rats to build an implantable brain-computer interface.In order to study motor cortex neural decoding, a hardware system was designed for rats performing a lever-pressing task for water rewards. The hardware system consists of a chronic 16-channel microelectrode array, a headstage, a water supply installation, a neural signal and lever pressure synchronous recording module and a FPGA-based neural decoding module. The results of this experiment indicate that neural signals from rat motor coetex can be used to predicte the lever pressure, and rats can learn to control an external water supply installation directly only using their brain. The results of FPGA-based decoding algorithm are as accurate as the realisation of Matlab, but the running speed is about 40 times faster.A portable telemetry system for brain stimulation was designed to study the influence of MFB electrical stimulation in free behaving rats. The results indicate two conclusions:the first is that the electrical stimulation of MFB initiattes and motivates forward locomotion, and the other is that it also causes different leves of activation between bilateral limbs. The exploration of this experiment will be beneficial to study electrical stimulation feedback technique in implantable brain-computer interface.The originality of this thesis is proposing and realizing a FPGA-based probabilistic neural network method for motor cortical neural decoding. In the FPGA architecture, training data of the network were stored in random access memory (RAM) blocks and multiply-add operations were realised by on-chip DSP48E slices. In the approximation of the activation function, a Taylor series and a look-up table (LUT) are used to achieve an accurate approximation. FPGA-based real-time neural signal processing technology research will contribute to practical use of implanted brain-computer interfaces.