Machining Process Of Silicon Carbidesingle Wafers And Its Surface Damage

Owing to high hardness and brittleness of SiC single crystal which has a good chemical stability, it is the critical issue that must be solved in its extensive application to obtain a wafer surface which is super smooth and free of scratch. Therefor, it has higher practical value to research the processing and characterization techniques for polished SiC single crystal wafer. In this paper,The parameters of processes are studied which include wire sawing, lapping and polishing wafers. By molten alkaline etching techniques and AFM, subsurface damage is removed; its thickness is measured as well. The efficiency and machined quality are improved.The main conclusions are showed as follows:(1).The SiC wafers off orientation can be controlled within±4% after sawing, The infeed velocity whose upper limit is affected by diameter and repeating use of diamond wire, decides the actual removal rate that is in the direct ratio to the wire sawing efficiency of SiC single crystal ingot.(2).The material removal rate during lapping processes is: 20-55μm/h in rough lapping,10-15μm/h in half-fine lapping and 4-6μm/h in fine lapping. The roughness of rough and fine lapping surface is about 220nm,143nm and 90nm respectively. (3).Single side polished wafers are brightness and transparent with double side polished samples. The mechanical polishing wafers were then etched in molten alkali, scratches and subsurface damage pits (SDPs) were observed in AFM images. The thickness of subsurface damage is about 65nm. Ra=1.1nm, Ry=1.4nm, Rz=39.9nm in an area of 2μm×2μm surface was obtained.(4).It was more effective to combine the techniques of mechanical polishing, molten alkali etch and chemical mechanical polishing for Ra=0.79nm, RMS=1.06nm,Rz=4.61nm in an area of 2μm×2μm surface was obtained, comparing with the surface quality by mechanical polishing. The AFM results showed: the thickness of subsurface damage is less than 10nm, using this method.(5).CMP technology combined with thermal oxidation was adopted to achieve near atomic-level flat surface with RMS=0.33nm, Ra=0.42nm, Rz=1.1nm in an area of 1μm×1μm. But the lattice defects on the surface were enlarged for a higher oxidizing rate, so this method is propitious to SiC wafers.