Design, Debug And Operation Of HLS Digital Low Level System

The thesis is about the design, off-line testing, unloaded testing and on-line adjusting of HLS DLLRF system. Following is the research contents:The design framework of HLS DLLRF system is completed, including three down-converting paths with three ADCs and one up-converting path with one DAC. The frequency of25.5MHz is adopted as the IF signal, the frequency of20.4MHz is adopted as the clock signal of ADC, the frequency of81.6MHz is adopted as the clock signal of DAC. A&P loop and tuning loop are built in the controller, which are used to adjust the A&P and frequency based on the signal difference.A test system is assembled to the DLLRF system off-line testing. It turns out that the loop gain is30dB at the frequency of100Hz and25dB at the frequency of1kHz, the loop bandwidth is about20kHz.After the off-testing, the unloaded testing is implemented in the RF system. By adjusting the attenuation and the gain, the higher loop gain is attained; the loop gain and loop bandwidth are set to25dB and5kHz respectively so that the RF system has a better stability; the unloaded amplitude and phase stability of±0.1%and±0.1%are achieved.After that, the on-line testing with beam is implemented in the Hefei light source. The adjustment of A&P loop and tuning loop are completed, the Kp and Ki of A&P loop are set to0.0001repectively, phase offset is set to-40°, loading angle of tuning loop is set to15°. In order to make the4th harmonic cavity more stable, the loop gain is adjusted to15dB. By optimizing the DLLRF parameters with beam loading, the maximum beam current of460mA is accumulated in the storage ring, the300m A TOP-OFF operation is implemented, and the beam-loaded amplitude and phase stability of±0.2%and±0.2°are achieved.In addition, in order to guarantee the running of RF system, a monitoring system, which is used to monitor the DLLRF, SSA and cavity tuner, is implemented by Lab VIEW in the RF system. Once the device breaks down, the loop will be cut off.