The Digital Control Technique Research Of Cascaded Multilevel Converter Based On Carrier Phase-Shifted SPWM

With high power electronic equipment increasingly applied, deeply studied is being done in this field. In these power equipments, there is a sharp problem, which is the in+crease of the power level and the improvement of the switching apparatus frequency. CPS-SPWM technique is the novel technique to solve this problem.In this paper, some research has been done to the digital control cascaded multilevel converter based on CPS-SPWM technique. By exploring to introduce microcontroller to the control system of power electronics, the digital control of power converter is being improved. Besides, the working model has been canalized detailedly the probability of integrating cascaded H-bridge topology and CPS-SPWM technique which is controlled by digital system bas been improved by a three-level and five-level output. By the spectrum analyzing, the result is drew: the CPS-SPWM technique counteract the low switching harmonics to increase the equal switching harmonic while swift the harmonics to the high frequency zone simply. The sampling way effect the contents of switching harmonics largely. In may paper, a asymmetry sampling way bas been application in a five-level converter. By this way, it needs double data but diminish the most irregular switching harmonics in the low frequency zone.In this paper, one phase five-level,seven-level, nine-level power magnify has been realized through CPS-SPWM technique based on DSP+CPLD hardware platform. The THD(total harmonic distortion), the transmission bond, the competition to realize and the application of every multilevel output is analyzed. A digital PI control closed loop system of five-level converter has been applied to a SAPF system and the offset current is ideal. The three-level dead-time effect is analyzed detailedly and through the dead-time offset, the net side current of three-level APF converter improved further.By a asynchronism transmission way from DSP to CPLD, a three-phase five-level pulse have been generated. It reduces possibility of the wrong pulse and inverse the reliability of the whole system. Otherwise, several dead-time generation way in digital system is discussed, analyzed and contrasted. What's more, the research of serial communication for DSP and CPLD has been done. By the SCI ports of LF2407 DSP, in the six meter experiment, the mis-transmission code duty reduce to zero. It provides a new idea to reduce the EMI from power circuit to the microcontroller.