VHDL Realization Of SVPWM Signal Generator

Space vectors pulsewidth modulation (SVPWM) utilizes the switching of the inverter's space voltage vector to get quasi-circle magnetic field, so the modulation can make the alternating current machine obtain better performance than sine pulse width modulation (SPWM) under a relative lower frequency (l³kHz). Applying the SVPWM control technology to the inverter control system will win better voltage output waveforms than normal six-step mode. The availability of volts d.c. may be increased by 15.4%, the switching loss may be reduced by 30% averagely under the same waveform conditions , and the dynamic performance is better. Therefore, the technology has become a hotspot issue.The thesis first clarifies the SVPWM theory and discusses the characters of three SVPWM methods according to the different inserting locations of the zero vectors, and chooses eventually the F₀ (000) V₁ (100) V₂ (110) ^V₁ (100) V₀ (000) inverter switches' order to synthesize the space voltage vectors. According to this method, the SVPWM signal generator IP core is designed top-down. The IP core is divided into six modules including frequency divider module, pulse width order generator module , basic voltage vector acting time calculating module , overmodulation control module, SVPWM signal generator module and dead zone delay module. The basic voltage vector acting time calculating module, overmodulation control module and SVPWM signal generator module realize the function of the calculation of basic voltage vector acting time, time data reconfiguration and the transform from time signals to pulse control signals, respectively. And the three modules are the key of the system. The short circuit of the inverter's bridge is prevented by the deadtime insert effectively.And then, the simulating waveform proves that the design in the thesis can control the inverter's bridge switches effectively.In the end, the thesis is summarized.