Analysis And Implementation Of On-Chip Transformer For RF ICs

The wireless communication revolution has accelerated the development of fully integrated CMOS transceiver. Following the Moor's Law, the voltage of the System on Chip (Soc) has been decreased, which has spawned a revival of interest in the design and optimization of on-chip transformer.On-chip transformer can couple the signal into the next stage without decreasing voltage swing and introduce the feed back with good noise performance. Furthermore it is the building block in QVCO.Recently the on-chip transformer has been used wider and wider in RF front-end circuits. Lacking of a general and accurate model is the barrier in RF IC design. It is inadequate to model the transformer by the analysis of on-chip spiral inductor.In this paper, a novel on-chip transformer model has been presented. By analyzing the electromagnetic field, those important parasitic capacitances which improve the reliability and accuracy are described in this model. This model can also offer the engineer an intuition in design and optimization of transformer with the standard CMOS process.Adopting TSMC 0.25μm Mixed signal CMOS process, various transformers with different parameters have been implemented to prove the accuracy and reliability of the model presented in this paper.Furthermore, a low voltage supply low noise amplifier (LNA) with the feedback introduced by transformer has been implemented by the art-of-state process (TSMC 0.25μm Mixed signal CMOS process). This LNA is achieved low noise performance with low voltage supply.