Research On The Memory System In SoC Real-Time SAR Imaging Processor

Synthetic Aperture Radar is a type of high-resolution microwave imaging radar. Real-Time SAR Imaging Processor on satellite is an important topic of research. In this dissertation, the architecture and the design of memory system in SoC real-time SAR imaging processor is deeply studied.New architecture of the memory system is proposed in this dissertation. In the real-time SAR imaging system, the data always are accessed both in row and in column; General DDR-SDRAM system can not meet the real-time requirement. This dissertation proposed special memory system architecture. The whole memory access efficiency of the new memory system was as 2 or 3 times as that of general DDR system.The high-speed memory control IP (Intelligence Property) is also designed in this dissertation. The throughput of the memory system is critical to the imaging system. In the design of this IP, some methods have been used to reduce the overhead of memory access. These methods involve: embedding a variable data-width FIFO to cache the write-back data; selecting best method of managing the access of every row in the memory; supporting some features of PLB bus which fit the SAR imaging processor best.The reliability of the SAR imaging processor on satellite is of great importance. A memory architecture in which most faults can be tolerant is proposed in this dissertation. When there is no fault in the memory system, the redundant memory module can be used as the error correction (such as Hamming Code). When there are some faults in the memory system, the redundant memory module can replace the fault module flexibly. Thus the reliability of the memory system can be improved significantly.