Research On The Common Mode Voltage Of High Voltage Variable Frequency Driver And Electronic Power Transformer

High power electronic technology has been widely applied to power system in recent years. High voltage and high-power variable frequency drive (VFD) technology is an effective method to resolve the waste of energy of traditional AC drive system. Electronic Power Transformer (EPT) can meet many new requirements of future power system.When the inverter works as the power supply of the inductance motor, the resulting common mode voltage (CMV) of converter brings lots of negative aspects to the motor. It reduces the life of the motor and increases industry cost. Researching on the characteristic of CMV and its restrain methods makes important sense.The paper introduces the buildup and working principle of the high voltage and high-power VFD, and points out the advantages of the universal converter of AC-DC-AC, introducing several kinds of structures that have been used rifely. The mechanisms of CMV being produced in two-level and three-level inverters in the universal converter have been analyzed. On the base of analysis of the common mode circuit, the relationship of CMV between the motor and the inverter is educed. So we can just study on inverter's CMV instead of motor's CMV. On the aspect of restraining CMV, two sides can be taken for presentations of the measures, one is hardware method, and another is software. Thereinto, hardware methods include two parts: active method and passive method. In this paper, some typical hardware measures have been introduced, also the principle done. On the side of software, the measures of depressing and canceling CMV have been presented. Aiming at the three-level inverter, Sinusoidal Pulse Width Modulation (SPWM) strategy and Space Vector Modulation strategy have been researched to suppress CMV. This paper also tries to investigate the effects of SPWM dead-time on CMV in VFD with three-level neutral point clamped (NPC) inverter. The CMV expressions of the NPC inverter without snubbers and load under different dead-time insert modes are deduced and analyzed. The impacts of the SPWM dead-time on the output voltage and the CMV of the inverter with RC snubbers and inductance load are studied. Finally, Simulations are carried out based on MATLAB.At last, the paper presents EPT's basic principle and characteristics, supplying a typical topology of EPT. Based on this structure, the creation and cancellation of EPT's CMV has been discussed. After analyzing a strategy that can be used to cancel EPT's CMV at ideal case, the localization and defect of the proposed method are brought forward and relative spare work has been prospected.