Test Condition Investigation In ESD Charge Device Model

Existing CDM ESD standards provide limited information and guidance on the parameters required to obtain repeatable, correlated waveforms. It has been shown that certain test condition associated with the CDM verification module play a significant role in obtaining meaningful results with CDM simulator. Discharge peak current is one of the most important specifications for ESD CDM test system. This paper set up examination to research the rule for test condition change which affecting the discharge current with CDM simulator. Data collection shows that during the verification process, detailed test condition of configuration (such as diameter, length and pin head shape of pogo pin and thickness of under COM dielectric layer) affect discharge waveforms. Statistical data for each test condition variation are analyzed and these results are well explained according to an equivalent RLC discharging circuit model. Experiment result show that circuit inductance and capacitance is the major factor which effect discharge peak current. In addition the shape of pogo pin will effect the current distribution. Base on this investigation, repeatable and correlated waveform meeting related standards can be ensured.