Analysis And Study Of Suppression And Effections Of Parasitic Parameters On Circuit Performance Of High Power Multi-level Inverters

From research to engineering applications, the high power equipments of power electronics gained both social and economic benefits. But in the research of high power multi-level invertors, effects of circuit nonidealities on circuit reliability are important, especially in engineering applications. The power losses and thermal management, parasitic parameters and circuit transient processes, multi-level voltages balance methods etc. have become key problems of multi-level invertor research and applications. This thesis's works are all based on this background.The system temperature rising and heatsinking design are determined mostly by power losses. This thesis presents the working states of three-level inverter, and promotes a method to calculate the power losses. Calculation results of the power losses of the 630kW three-level invertor indicate that water cooling would be effective and practical. To restrict the high di/dt and du/dt, a diode-clamped three-level inverter topology with RCD snubbers and the design rules are proposed. According to the simulations and calculations of the snubber circuit, the influence of snubner circuit parameters upon turn-off characterristics of IGBTs are presented.To consider the circuit parasitic parameters, the circuit stray inductance has serious influence upon the turn-off characterristics of IGBTs, including turn-off voltage spikes and transient time. Especially in high power inverters, di/dt and du/dt are high in power devices, the components of the inverter will be damageed. The working stages of the IGBT turn-off transient processes, the equivalent circuits of basic loop of the three-level inverter with stray inductance, and the influence of stray inductance are proposed. The simulation accuracy of the turn-off voltage spike is proved through calculation with the equivalent circuit.IGBT voltages unbalance of the NPC three-level converter is analyzed, then the advanced circuit methods to balance IGBT volatges are provided. The clamped resistor method was proved to be effective. To reduce stray inductance and optimize the turn-off characterristics, a three-level Bus bar with minimum inductance is presented.A lot of simulations are done in the proposed researches. To prove the research results above, a prototype of 15kW diode-clamped three-level inverter is implemented. The reserches above are much critical to the applications of high power multilevel inverters.