The Research Of Merging Unit In Electronic Tranceducer Based On FPGA Chip

With the improvement of electric power system capacity and the increasing of the level of the running voltage, the traditionary electromagnetic transducer is difficult to satisfy with the need of the digital and automation power system. So more and more people focus on the new electronic transducer. In this paper, the author discusses the realization of the digital interface of the merging unit (MU).Firstly, the author summarizes the development and operation principle of electronic transducers, makes the whole design, and then introduces IEC 60044-8 and IEC 61850-9-1. On this theory, the author puts forward a project which based on Nios II FPGA. After the introduction, we make the hardware design and the software design, and finally carry out each module.This thesis analyzes the new international standard in detail which is still under research.The novel design introduced in this paper succeeds in introduing the conception of research and develop environment that is convenient to expand the functions of the system.This system is based on the FPGA system in which embedded Nios II core.The system can greatly meet the transport and compute demand.Also,it cuts the cost and shorten research cycle by making use of the SOPC technology.This design is good at solve these problems such as processing many task at one time, large communication information flux, high communication speed and so on. It has upper reliability and real time character and provides the way for future research of the MU in the electronic transducer.