Research And Design Of Cascaded Multilevel Inverter Based On DSP And FPGA

Multilevel inverter structures are becoming increasingly popular for high power applications in modern power electronics technology research. Among them, the cascaded multilevel inverter is based on a number of basic cells (i.e., H-bridge inverter) connecting in series to form a single-phase or three-phase inverter. Each basic cell can produce square voltage wave or step voltage wave, and create more level steps of the wave to approximate the sine output voltage through the superposition of the output waveform synthesis. The inverter is constrcted by the basic cell in series to complete the high voltage power output. Compared with non-cascaded circuits, the switch component's power and voltage stress of cascaded inverter are not limited. Meanwhile it can decrease dv/dt and achieve improved harmonic performance for the modulation of cascade inverters. As the advantages mentioned above,in recent years, the cascaded multilevel inverter has attracted great attention in the application areas such as high power converters, AC drives, and power active harmonic filters. It is becoming the first choice in the high voltage energy conversion applications.This paper introduces the theoretical analysis, system simulation and actual experiments of cascaded multilevel inverter,design a 5 level cascaded H-bridge multilevel inverter hardware experimental platform based on DSP and FPGA. The main controller, TMS320LF2812 DSP, is responsible for the whole system control, and EP1C6T144C8, the coprocessor, realizes the digital PWM module and produces multichannel PWM driving pulse. Then it controls the H-bridge driver chips EXB841 to drive IGBT main circuit.Firstly, this paper introduces the multilevel inverter topology and the PWM control strategies, chooses the cascade multilevel inverter as the object of study, analyses the phase shifted carrier PWM control strategy of the output voltage and harmonic, and verifies the results through MATLAB/Simulink simulation algorithm. Secondly, this paper designs the IGBT main circuit and DSP and FPGA control circuit, direct, using digital frequency synthesis design for a common PWM modulation module in FPGA, then realize a PWM channel expansion. Finally, the experimental results are given.