| Electronic products play an important part during people daily life, it becomes an agent problem to supply more precious and more stable power. This paper focuses on digital control, combined with analog circuit. A digital control power management chip based on low power PVT (process,supply voltage and temperature insensitive) ring oscillator and MPMF (multi phase & multi frequency) modulate is designed. The chip can keep a stable output while temperature ranges from 0℃to 100℃and the power voltage ranges from 2.8V to 3.8V, and achieve a stable high efficiency by MPMF modulate.This digital control power management chip is implemented on Chartered 0.35μm 3.3V 2P4M CMOS process. Ring oscillator circuit design was implemented with Cadence Virtuoso, managing the post-simulation and tape-out verification. The experiment result showed that the chip stability and power cost have significantly improved. As deviation compensation technology was used to achieve high performance in stability and power consumption. The tolerance of output switching frequency to variation in process,supply voltage and temperature was improved by compensation technology without voltage reference. The cycle value was adjustable for the compensation method to delay cell. The simulation of Mentor Carlo proved that the variation of frequency caused by process variation was decreased to 40% compared with uncompensated value. And experiment results showed that the frequency of ring oscillator achieves within±3.22% variation while temperature ranged from 0；℃to 100℃and within±3.36% variation while the power voltage ranged from 2.8V to 3.8V, and. The supply current of whole chip at supply voltage of 3.3V was 950μA.The digital pulse width modulator was coded and simulated in modelsim, synthesized in Design Complier and place & route in Astro design tools. The post simulation and tape-out verification are managed. And experiment result showed that the linearity of digital PWM get obvious improvement by the optimization of critical path. And the outputs of twelve phases were fit with the frequency choice input, keeping the phase difference with the variation of output cycle. The measured results showed that the DPWM resolution was about 11bit at the output frequency of 0.9766MHz,10 bit at 1.953MHz,9 bit at 3.83MHz,8 bit at 7.93MHz and 7bit at 15.34MHz according to the load current. The power consumption of the whole chip was 13.2mW from the 3.3V power supply when the output frequency was 0.9766MHz. Finally according to the parameters of chip, a digital PID compensator is designed with bilinear transformation method to compensate the control loop. Besides the system including bias voltage compensator circuit, ring oscillator, analog-digital converter, digital pulse width modulator, digital proportion integrated derivate compensator, power MOSFET and LC low-pass filter is modeled in simulink and simulated. The simulation result shows that with the digital control loop, at the switching frequency and load variation, the system remains a stable output voltage, achieving a small settling time and load regulation.
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