Design Of Low Dropout Voltage Linear Regulator With Low Quiescent Current And High Stability

With the rapid development of power supply technology today, high-performance, low power consumption and high stability power management projects have become the necessary considerations for the design of various types of portable electronic products. On the basis of the theory of the low dropout linear regulator,the thesis built an overall framework of low dropout linear regulator and set design specifications of the chip. The entire low dropout linear regulator system, including band-gap reference voltage source (Bandgap), error amplifier (Eamp), bias circuit (Bias-gen), as well as enable circuitry (Enable) and so on, was designed.The CSMC 0.5μm CMOS process was used to design the LDO. The whole chip and its sub-blocks have been designed by Cadence's Composer and Virtuoso. The circuit simulation was carried out by Spectre. The results of simulation indicate that the drop-out voltage is just 300mV, the system working voltage is from 2.0V to 5.0V (typical input 3.3V), and the quiescent current is lower than30μA. In the temperature range (-40℃~ +125℃), the system maintains good stability and meets the design requirements. In addition, the low dropout linear regulator chip is integrated with an over-temperature protection circuit, an over-current protection circuit and an ESD protection circuit, so as to maximize the protection of system's stably operation.