The Research Of An New Method Of Logic Simulation For Complicated High Speed ASIC

Logic simulation is a necessary step in design of ASIC. With enlarging of circuits scale and speeding of clock frequency constantly, logic simulation is improving requirement constantly in tine consuming and accuracy. Simulation of digital circuits is based on computing of logic and delay for component in circuit netlist, so for obtaining correct simulation result, I must have logic computing correctly and delay analysis accuracily. Logic computing is Boole expression-based computing on level. It can realize simulating the instantaneous state of digital circuits. But it cannot simulate circuits continuously which have complex delay properties. Though delay analysis can describe the time properties of circuits, it separate logic computing, so it can not simulate the behavior of circuits on time. As simulation tools for digital, they are not complete.Boole Process Theory is a new method that was advanced recent years for describing and analyzing circuits. It induces logic and delay to waveform, and describes the continuous states of nodes in netlist by waveform. It can realize simulating continuous states for integrated circuits by computing waveforms. So we can simultaneously simulate logic functions and delay properties of digital Circuits really by description and computing methods that are based on Boole Process. This dissertation use the concept of waveform and the defines of waveforms computing to set up reality-closes simulation model, and puts forward a new simulation algorithm, which realizes simulating digital circuits more accurately under high clock frequency and large scale integration. The outstanding superiority of my algorithm is that it can obtain complete simulationinformation of components constantly when the simulation is having. So this algorithm settle the problem that traditional simulation methods cannot obtain complete simulation information of any components before the simulation comes to an end. Thus it raises the efficiency of simulation. At the same time, the dissertation discuss some important problems in simulation and verification in detail, such as hazards finding, inertia delay, feedback treatment, false paths discerning, setting up and holding time, critical path and shortest path. For above problems, I design Boole Process-based algorithm. For example, Hazards Finding Theory work out a formal method of finding hazards by waveforms computing; Waveforms Increasing Algorithm settle the defect of Boole Process in feedback cycle treatment; False Paths Discerning Algorithm can delete useless nodes in netlist effectively; Inertia Conflict Eliminating Method describes the state of nodes truelier and reduces computing.