Massive Parallel Test Strip Handler Design For Logic Devices Final Test

Final Test of semiconductor IC is a necessary and important process ofsemiconductor manufacturing, and an automated test handler is semiconductor-manufacturing equipment that presents integrated circuit (IC) devices to an automatedelectrical tester. As two main roles that dominate IC testing cost, tester and handlershould all contribute their own maximum capacities in order to achieve the objective oftest cost reduction. After theoretical study and analysis on IC test cost, this article found out a best wayto reduce IC testing cost from increasing related equipment utilization, designed andfabricated a new strip handler for massive parallel test of digital IC in order to maximizetest parallelism capacity of an advanced digital tester. Meanwhile, increased the handlerutilization of it own as well through optimizing each module's mechanism design, andgreatly solved the task of test cost reduction through both aspects of tester and handler. At the beginning of this article, compared and optimized every necessary functionmodule from many common mechanism in order to achieve the best utilization of eachown. On the basis of that, set up an optimizing global construction of this strip paralleltest handler. Then, proceeded to get key parameters from corresponding experimentsand designed the details by using a SOIC28LD devices' x32 parallel test as the object.Adopted current advanced simulated DOE experiment and statistic optimization theoryto get the parameters, and applied these reliable results to the data base setup of this striphandler. Another, to ensure to get 6σquality for handler tested devices, we put moreattentions on design details and process flow for each functional module, and comparedthe test cost reduction result by using the data got from the new strip handler running onthe test production floor. Finally, summarized the future and prospect of strip handlerand parallel test for digital IC products.