The Study Of Parallel Architecture In Application Specific Integrated Circuit And Practices In Video Decoder Chip Design

With the continuing developments of multimedia and wide-band network technology, much higher efficiency in multimedia dada compression and real-time applications are required. High-speed video decoder is a key component of high definition television receiver. The target of high-speed video decoder is to decoder very high-speed bits real time, and the key is how to improve the parallelism of video decoder. This paper studies the parallel architecture of high-speed video decoder by the force of parallel processing technic.There are two kinds of parallelism: spatial and temporal. In the part of parallel architecture of high-speed video decoder, we study and analyze the parallel processing techniques in depth, compare the differences and performance, and point out their applications in video processors. Only with the match of the parallelism of algorithm can the parallel architecture work best. This paper gives a multi-level parallel structure of video decoder by analyzing the parallelism of video compressing algorithm based on hybrid coding which is widely accepted by most video compressing standard, and decoding missions. We partition the decoding mission from two sizes, coarse-grained and fine-grained, spatial and temporal.In the all kinds targets of video decoding, Variable length decoding belongs to serial operating with many judge branches. Table look-up can be used to accomplish this kind of operating well by calculating all the possible results first and storing them in memory by table format. As a result, serial operating can be replaced by parallel table look-up operating. Partitioning large tables into several small tables and looking up these tables simultaneously can raise parallelism further. Parallel table look-up requires that the input data must be prepared parallel. This precondition can be accomplished by reconstructing the variable length code table and barrel shifter. All the above measures ensure that one variable length code can be decoded in one clock, which meet the demands of real time decoding.Except many judge branches, complex computing is another characteristic of deblocking filter. Adaptivity of deblocking filter brings judge branches. The Adaptivity appears in three levels: Edge Level, Slice-level and Sample-Level. Judge branches aren't advantageous for general processor. But we can do these better by use both temporal and spatial parallel technologies during dedicated filter circuit design. 1-D edge filter is the kernel of deblocking filter. Only one edge filter is used in our design by proper data storage and scheduling, which facilitates the reducing of resource expenses.