Design And Implementation Of The High-speed Digital Circuit Demo System

Currently, with the rapid development of integration and interconnection technology, the data transmission rate of inside-chip, chip-to-chip, and board-to-board has been increased greatly. At high speeds, logic signals often appear hairy, jagged and distorted because of fast signal rise and fall time. We must avoid these phenomena in the high-speed digital circuit system. Signal Integrity (SI) problems have become a hot topic in the high-speed digital system. As the need for higher bandwidth accelerates, digital designers choose differential signaling to satisfy high bandwidth requirements while reducing common-mode noice. The differential data transmission method used in LVDS (Low Voltage Differential Signaling) can reduce system cost through fewer pins, cheaper PCBs, smaller connectors, lower EMI, better signal integrity, low power and noise immunity. This thesis focuses on the design and implementation of the high-speed digital circuit demo system. In this paper, we firstly introduce several typical SI problems in the high-speed interconnection design, then introduce the characteristics of LVDS, after that put emphasis on the design and implementation of the demo system, give the design rules, scheme and implementation of each functional module, lastly present the measured waveforms of eye pattern and the BER performance of chip-to-chip and card-to-card data transmission. The measure results satisfy the expected design specifications.