Research And Realization Of Audio Algorithm On Digital Television Source Decoder Chip

With the quick development of deep sub-micron semiconductor technology, more and more SOC(system on chip) have been developed for real-time systems. Digital Television is developed from analog television to achieve high resolving power of image quality.DTV integrated source decoder is a key component of high definition television receiver. In this thesis, with the goal of audio decoder's design in DTV source decoder, we research and optimize the algorithm of audio decoder, and give the strategy of audio decoder's design based on the RISC core.The design process of SOC is to map decoding algorithm for TS (Transport Stream) , video and audio into processor design space. Integrating TS De-multiplexing, video decoder and audio decoder into single chip with embedded RISC core is the trend of DTV source decoder design. The embedded RISC core of our source integrated decoder is ARM920T, which not only be responsible for the control of the whole system, but also take on the algorithm task of TS Demux and audio decode. In this thesis, we give the C language Co-debugging strategy of every modules in DTV source decoder, and describle the realization of audio decoder code in Co-debugging. Furthermore, we also give the DTV source decoder's verification method based on Altera FPGA.There are many audio coding methods currently, such as MPEG-1 LayerIII (MP3), MPEG-2 LayerI LayerII, MPEG-2 AAC, Dolby AC-3, MPEG-4 AAC and so on. The audio compress standards applied in the popular standards DTV are: MPEG-2 layerI and layerII in DVB, AC-3 and E-AC-3 in ATSC. In this thesis, by researching the DVB audio decoder's algorithm, the shortcomings of the sub-band synthesis filter which is suggested by MPEG standard is analyzed. By observing the bit-allocation and dewindow coefficient tables in MPEG standard, these tables' datas stored in the code are optimized by their repetition and odd-symmetric character. To reduce the computational amount and memory size, the algorithm and the flow of sub-band synthesis filter has also been optimized. Then DCT fast algorithm can be used.By refering to other's fast algorithm, 32-point DCT and four 8-point DCT transferred from 32-point DCT has been used in the audio decoder. All of these make the computational amount of the whole sub-band synthesis filter reduce about 60%.Being a 16/32 bits high performance, low power and low cost embedded RISC micro processor, ARM has been used widely in embedded region. In this thesis, the whole design flow of the audio decoder for DTV(for DVB) is described:coding with full precision first, then fix-point transfer with limited precision. Then the ARMulator software simulation based on ARM920T core and the real-time decode design on the development board based on Samsung S3C2410 ( ARM920T Core) are described in detail. Decode speed and performance is the most important parameter to evaluate the audio decoder. Based on the test of some representational audio streams, the decode speed and SNR of various audio decoders based on various algorithms are compared in table format.