New Structure And Device Performance Research Of Sub-100nm SOI MOSFET

Silicon-on-insulator(SOI) device has the advantages of small junction capacitance, good resisting-radiation property, superior subthreshold characteristics, eliminating the latchup effects, suitable to low-voltage low-power operation, etc. It is known as "the 21st silicon integrated circuit technology". In this paper, the SOI technology and its fabrication process are introduced briefly. Then, the challenges to sub-100nm CMOS devices are discussed, such as quantum confinement, carriers random-distribution confinement, the increase of all kinds of leakage current, the dagradation of carriers mobility and the increase of source-drain series resistance. Secondly, the new structures of sub-100nm SOI devices and their design flexibility and friendship are introduced. Lastly, adopting device simulation software MEDICI, and revising the relevant models in the software, the impact of device dimensions on device performances are discussed, such as threshold voltage, subthreshold slope, turn-on/turn-off current. The research results indicate, with the gate length fixed, the device performances vary slowly with larger buried oxide thickness; while when the buried oxide thickness less than 40nm, the performances of the device vary rapidly. The result shows that the front-back gate coupling effect increase with smaller buried oxide thickness. On the other hand, increasing the channel dopant and decreasing the silicon-film thickness, the performance of the device will also be improved. This shows that the impact ionization effect increase with the decreasing of silicon film thickness. At last, based on the simulation result, the optimization of the device dimensions are gived, The design permitted region of the feasible silicon film thickness and the feasible channel doping is also given.