The Research Of VLSI Functional Test Based On Parallel DSP

With the diverseness requirements of the function of VLSI products, VLSI industry developed by leaps and bounds. Various VLSI appeared, these VLSI have different function and their working speed and number of pins are hardly same. These facts add more difficulty on VLSI functional test. To realize test various VLSI in one system, we must develop a kind of testing equipment which has a faster testing speed and more test pins. This paper illustrates the working principles and advantages of pattern generator used in VLSI functional test based on multi-ADSP-TS101s. Through the analysis of parallel computing and parallel computer, this paper proposes the plan of parallel ADSP-TS101s based on the software & hardware resources of ADSP-TS101, meanwhile gives the comparison of different plans. In addition, the detailed analysis of some frequently used memory test algorithms and brief analysis of some test generation algorithms for VLSI are also included in this paper. This paper is described in five parts as follows: Firstly,parallel computing and parallel computer are expatiated. We introduce the development of parallel computer, and parallel algorithms & the sort of parallel computer. Secondly, the functional test of memory is introduced. We analyze the structure of memory, given the cause of fault, some frequently used memory test algorithms, and the simulation result. Thirdly, the DSP used in our system is expatiated. Based on the software & hardware resources of ADSP-TS101, the plan of parallel ADSP-TS101s is given. Fourthly, the VLSI functional test is introduced. We analyze the development of automatic test system and some test generation algorithms for VLSI. . Fifthly,the plan of pattern generator used in VLSI functional test based on multi-ADSP-TS101s is given.