Research And Implementation Of Key Technologies Of System Bus In X Processor

With the development of microelectronics, the current high-performance processors are made in 0.13um process widely, and the clock frequency of processor core is above 3GHz. However, the bandwidth of off-chip memory and peripherals is much lower, and the gap is enlarging. As an external interface of the processor, system bus component affects the efficiency of memory system directly. Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.Modern high-performance processor can exploit more parallelism. As one program stops due to waiting for memory data, processor can choose to run another program. Thus, it is more important to provide continuous data stream than to reduce the delay of single memory access. According to this principle, system bus component of the current high-performance processors is implemented by the split transaction bus technology, in which each transaction is split to several phases, and the different phases of transactions are pipelining. By this means the split transaction bus can deliver data to processor core continuously. We study the split transaction pipelining technology in detail, and apply it to the implementation of system bus component in X processor. The bus and the processor core often run in different clock frequencies, so their interface signals belong to different clock domains. This will bring on the signal transmitting delay. In this situation, it may result in that the internal Cache returns wrong snooping result because the internal Cache cannot get the conflicting information in time when the snooping transaction conflicts with the returning transactions. In this paper, we propose one re-snoop mechanism to solve the snoop unconsistency problem.To improve the performance of system bus and increase utilization of the transaction pipeline, we reform the data transfer protocol, so that it can increase the source synchronous data transfer rate from 2 times to 4 times, which makes the data phase no longer the bottleneck of the transaction pipeline. The performance tests of the reformed system bus component show that the performance of system bus is highly improved.The research of system bus protocol and implementation of the system bus component of X processor are significantly important to improve the performance of our 64-bits X processor, and this paper is also a preferable reference to explore system bus protocol of the next-generation high-performance processors.