Study On DSP-based Underwater Video Coding System

At present, with the improvement of human ability to explore the sea and the urgent need for the development of marine resources, deep-sea exploration and operation technology has become very important in the field of marine research and development. In deep-sea exploration and operation, the most commonly used method is video and image observation based on underwater robots (ROVs/AUVs). Video and image observation is the most direct, vivid and effective method for deep-sea close observation. In order to overcome the limit of transmission bandwidth in the underwater acoustic channel, underwater robots have to equip with efficient underwater video coding system. The system can capture massive underwater video, process efficient fast compression and coding based on the characteristics of underwater image to meet the real-time requirements. Therefore, according to the characteristics of embedded systems, this thesis employs a highly efficient underwater coding algorithm, and designs a stable and reliable underwater video coding system.The main research work includes the following two parts:(1) The design of the underwater video coding hardware system. In order to ensure not only the real-time coding, but also the stability, scalability and etc. of the system encoding hardware, the system is based on the hardware platform architecture of the combination of DSP (TMS320DM642) and FPGA (Cyclone II EP2C35). The DSP is responsible for execution of algorithm, control of driver programs, scheduling of software threads and so on. The FPGA is responsible for the communication between the system and the external circuitry (such as acoustic communication module, hard disk, SD card) through a flexible expansion interface. As the core of the system, video processing module consists of video decoder TVP5150AM1 (responsible for composite video signal input), video encoder SAA7121H (responsible for composite video signal output) and video DAC ADV7123 (responsible for VGA signal output).(2) Driver development, algorithm transplanting, and optimization of the underwater video coding system. Based on DSP/BIOS real-time operating system, design application overall framework, which consists of hardware interrupt (HWI), task (TSK) and background idle thread (IDL). Based on the characteristics of TMS320DM642 DSP video port peripheral, common DSP video port peripheral driver is modified. Verilog hardware description language is used to design FPGA hardware logic, which connects DSP and underwater acoustic communication module with each other, and DSP controls the watchdog timer through FPGA hardware logic, when the system software encounters abnormal situation, the reset chip reinitialize the system. The underwater video coding software system developed in the VC++ 6.0 platform is transplanted to DSP embedded platform, and various DSP optimization techniques are comprehensively used, such as compiler options, intrinsics, loop unroll, linear assembly and so on. Average algorithm coding time after optimization is only about 30% of that before optimization, which remarkably improves the real-time characteristic of the system.Experimental results show that:the underwater video coding system can achieve a compression ratio of 250:1-500:1 as for common seabed video of QCIF (176×144) resolution at the average frame rate of 8fps with acoustic transmission, and can stably process underwater video compression and transmission of high compression ratio.This research project is one of the key techniques of underwater robots, and has an important research value and broad application prospects for deep-sea exploration and development.