Design And FPGA Implementation Of Decoders For Rate-Compatible QC-LDPC Codes

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have received tremendous attention in the coding community because of their excellent error correction capability and low coding and decoding complexity. Combining the existing theoretic and practical fruits, researchers focus on the designing of powerful LDPC coders and decoders with low complexity.In this dissertation, some key problems of the codec for QC-LDPC codes are investigated by theoretical analysis and implementation. The main works are summarized as follows:1. The history and development of modern coding techniques are introduced, and the principles of coding and decoding algorithm for LDPC codes are systematically summarized. The property and method for constructing QC-LDPC codes are also derived2. The equations for updating messages in sum-product algorithm are derived in connection with the principles decoding algorithm for LDPC codes then we compared several reduced-complexity versions of BP algorithm to select a flexible form according to practical applications.3. Based on the layered decoding algorithm of Normallized Min-Sum Algorithm, the FPGA implementation method of decoding for QC-LDPC codes is proposed, the rate-compatible decoder we design can reduce decoding complexity and save hardware resources.4. A decoder structure with further improved decoding throughput is proposed, greatly accelerate the decoding process and convenient for high speed decoding.