Realization Of Adaptive Floating-point Multiplication, Division And Square Root Unit For Single, Double And Extended Precision

FPU (Floating Point Unit) is commonly used as the dedicated component in the design of modern processors. Since the applications of high precision, graphics acceleration and digital signal processing propose high requirements on floating point processing, FPU has become an important component of modern microprocessor. As the integrated circuit technology is developing rapidly, and the integration density has been improved greatly, floating point performance becomes a key indicator in evaluating CPU further to frequencies. The performance of the FPU determines not only the performance of CPU, but also the application fields of CPU. Therefore, the study on how to improve the performance of FPU has become a significant subject.This paper analyzes the operation principles and the formula of floating point multiplication, division and square root. After a deep study of the Goldschmidt algorithm based on Newton Iteration, this paper designs and implements the high-speed floating point division and square root operation unit, integrating the floating point multiplication operation into it successfully, this achieves in multiplexing the multiplier. The unit is adaptive with single, double or extended precision, and completes the operations of floating point multiplication, division and square root. In the hardware implementation, the ASIC full-custom circuit design method is taken and a simulation is completed using SMIC 0.13μm library. The result shows that the final frequency can reach to 380MHZ.