The FPGA Implementation Of RED Algorithm Based On Routers

As the rapid development of computer networks, the problem of network congestion was coming one by one. When network congestion occurs, network performance will fall,such as the delay intensify, the response time increase,the effective throughput decreased , and so on.So how to solve the network congestion is becoming a hot topic in people research. Congestion control is the strategy used to prevent and avoid the congestion. Active queue management algorithms are very important algorithm which are implemented in the router , RED algorithm included, the most classical algorithm. From the environment of algorithm implementation, there are two methods : WINDOWS environment and LINUX environment.LINUX environment is used for simulating a real internet environment. It evaluates the performance of an algorithm by a lot of simulation experiments. But because RED algorithm itself will occupy part of the router memory resources, it affects execution speed of the algorithm which results in network control can not work properly; WINDOWS environment implementation achieved RED algorithm by a variety of hardware and software in WINDOWS environment, improveing the operation speed of the algorithm, saving the resources that achieve the algorithm in the router,increasing resource utilization.RED algorithm achieves the purpose of avoiding network congestion by inspecting the average queue length of data flow and discarding packets with certain probability. In actual network , once the congestion is discovered , the router chooses sources to inform the congestion randomly which makes them reduce the rate of sending data before queues overflow to alleviate network congestion. The algorithm is based on the strategy of FIFO queue scheduling, and it discards the packets entering routers only, so it is used simply. The design of RED algorithm pursues four goals. First,the minimization of lost package rate and queue delay; Secondly, to avoid the global synchronous phenomenon; Thirdly, to avoid the sudden business prejudice.Lastly,to control the average queue length with no coordination of transport layer protocol, which can avoid congestion.The design is proposed based on the understanding and analysis of the algorithm's basic principle and implementation environment. It used for hardware implementation of random early detection algorithm independently in FPGA, and then passing algorithm results to the router by data transmission . RED algorithm is mainly divided into two formulas: a formula for calculating the average queue length, the second is the formula for calculating the drop probability. In FPGA circuit design, the RED algorithm is made into a standard mathematical model, achieved in five modules: calculating the average queue length module, packet processing module, random number generation module, the counter module, drop probability calculation module.Design details are mainly related to the way to store the variable, the register number,computing precision and the connection between the register and register signals and so on.The congestion control algorithm RED is widely used by people due to its relative low delay,big throughput ,and better fairness.In the design,through the waveform analysis of simulation experiments of the RED algorithm implemented in the FPGA,RED algorithm achieved congestion control management function,and in the whole design , the FPGA makes use of relatively less hardware resources, based on saving storage space for the router, implementing the RED algorithm rapidly and effectively.